Being able to "roll back" changes to caches came up a number of times during the talk and afterwards. Some processors already have this ability in the form of transactional memory, though I'm not sure if it extends to caches. Would it be possible to use something like this to help prevent side-channel attacks of this form?
It's possible that some of the processor design elements would be related. "Transactional memory" basically means keeping pending writes in a buffer until the transaction is committed; but that's only a small part of what you would need for security, since you also need to hold reads in a "pending" pool before they enter the cache.