Bipolar-Zener Combo Takes On CMOS | Hacker News Reader

Bipolar-Zener Combo Takes On CMOS

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Interesting, here is another link with some additional interesting points: https://www.electronicsweekly.com/news/design/tunnelling-tra...

What caught my eye was this tidbit.... "Analogue computing The last trick up SFN’s sleeve is Bizen analogue blocks – op-amps and comparators (in the PDK), and even analogue computing blocks such as a divider – the analogue computing blocks avoiding using logic – and thus the associated ADC and DAC – in certain applications. Using a coarse-fine architecture, Summerland is predicting 1μW 1μs analogue division instead of ~20 instructions and ~100 instruction cycles if logic was employed. This analogue processing capability is being branded IPU for ‘instantaneous processing unit’."

Analog computers making a comeback ? you never know.

I wonder if using this for low-precision floating point math in graphic cards would make sense.

Maybe it's a way to do realtime raytracing? Who cares if the results have a little noise? It can be even argued it gives it a special "look".

> Analog computers making a comeback ? you never know.

For dataflow paradigms like deep neural nets it makes sense. If it's significantly faster and significantly more power efficient, and the intermediate states are largely arbitrary weights anyway, what's the point of digital precision.

It's not the precision, it's avoiding O(n^2) physical connections per layer.

That's my point. Swapping digital for analog gives up the ability to know the precise bits of a register but in return you gain a lot in efficiency.

That's not what I'm getting at. It's not the nodes you need to worry about, it's the edges. If you've got two fully connected 100-neuron layers in a physical circuit, that's 10,000 wires you need to route, and they all want to cross each other. That's why nobody builds physical neural networks.

I guess all you would have to do is to make sure the precision was a few dB/bits more accurate than 16/32/64 bit floating point for a certain sigma probability and a lot of people would be perfectly happy with it.

I wonder if you could use it as an efficient starting point for various different integer division algorithms which rely on a rough starting point. For instance, it could be your X_0 estimate for (1/D) in the Newton-Rhapson method [1]. Or, potentially, as a high-quality first stage input for a successive-approximation approach [2].

This could allow you to get a rough approximation incredibly quickly and opt to refine it further using it as a high-quality input to speed up finding the "true" answer.

[1] https://en.wikipedia.org/wiki/Division_algorithm

[2] http://www.ijiee.org/papers/173-E0005.pdf

The trade off would be that your A-D converter would have to be fast enough as well as offer enough bits of result to give the iterative algorithm a running start. Digital video cameras would be the class of device we ~all have that does high-samples-per-second conversion. A 4K@60p camera has to do 500Ms/s at least so if you can allow that many approximate results per second then it might work out. There would also have to be a comparably fast DAC to tell the analog circuit what you want to approximate.

I think a more-complete computing engine in analog would be a bigger win, because there won't be conversion overheads. Or as was suggested somewhere in this topic, a field-programmable analog array.

Probably not analog computers. But analog circuitry, CPU, and power supply all in one package seems likely.

Analog computers are incredibly fast for solving some very difficult problems such as integration. I could see, if easy to implement, basically an "analog FPGA" hybrid of digital fabric and analog components for you to piece together.

You may be interested to know that FPAAs are a thing that does exist. https://www.anadigm.com/_doc/DS030100-U006.pdf

That's really cool, thanks for sharing!

They're also noise-sensitive, hard to calibrate, hard to reprogram, and only suitable for a fairly small range of problems. But nevertheless very cool devices.

Bloody awful things. I’ve built a few simple analogue PID loops and simple analogue computers over the years and it’s an art and a half. I think the biggest pain I had was before the availability of reasonably stable log converters was trying to use matched transistor pairs to perform log operations. Took three days to work out where an error was creeping in and it was from the thermal offset voltage of the buffer opamp input. The circuit was drifting due to my desk lamp warming it up. The IC was out of spec on drift too! :(

I did succeed in producing a four quadrant multiplier in the end but required some unholy things to be done.

That and noise and the cost of precision make it almost useless compared to a digital computer now. The rise of direct sampling SDRs confirms this. Crazy dynamic range, excellent noise floor and hardly any analogue up front.

The 4QM is one of the most useful analog devices in music synthesis, where absolute precision is unnecessary. There it's called a ring modulator because it emulates the sound of a bell. It produces both the sum and the difference of the two sinewaves fed into it.

Edit: Just looked up "ring modulator" on Wikipedia. It says the name comes from the ring of diodes in the canonical circuit. I'd always heard the genesis was from the bell-like sound it made. And there are better ways to build analog multipliers than four diodes in a circle.

Similar to diode balanced mixers in RF stuff.

Yep. It's a mixer in RF terminology. Or a heterodyne. Lots of names for this thing.

Try to find some analog device with 2\^53 signal to noise ratio, look how much it costs.

Then remember that this is only the ration on our most used digital numbers because it's easy and cheap. Applications that require precision normally go with a 2^113 ratio.

I thought some NNs actually used fewer bits (32?) than the normal 64bit floating point because it is faster and good enough?

On PCs everybody uses 64 bits, and if they choose not to, they have a large risk of being converted into and out of it all the time by the compiler because it's faster.

But specialized CPUs often get different number sizes. It's common for specialized NN and GPU hardware to use 32 bits floats, what leads to 2^24 definition that is actually around the top precision you will find for analog components on the places people (instead of labs) go for buying them, at least on the countries where access to those aren't restrict due to nuclear proliferation concerns.

Floats on modern PCs are 32bit (you can look that up if you want). Doubles (double precision floats) are 64bit and are seperated from 32bit. There is also half precision float (16bit) since quite a few generations.

There is no conversion happening on the compiler level unless you choose to run with soft-floats for reasons unknown.

You don't need specialized GPU hardware for 32bit floats either; that is the default. You need specialized hardware if you want 64bit floats however (CAD Designers love those). Half precision is also available on all GPUs that people will likely care about.

Some NNs use 16bit floats instead of the normal 32bit floats, because yeah, it's good enough to cover what you need from low quality images for example (you get around 12bit color space, which can be enough for a lot of things)

> Analog computers making a comeback ? you never know.

Analogue processing may be a superior alternative to GPGPU for implementing neural networks.

Nailed it: https://www.mythic-ai.com/technology/

I dispute this. The problem with analogue processing (besides noise, of course) is that the dynamic range sucks compared to plain old floating point. Fine for inference, not for training. And most of the compute power in NN is spent on training, inference is trivial.

Analogue processing has certainly been successful for people, so I wouldn't be too dismissive.

I would not be certain of the premise in your statement. We do not understand the brain well enough to say whether error correction (which is inherently digital) is utilized. There are some pretty solid clues that some of the processing in the brain is not analog (e.g. the step-like behavior of the activation function of biological neurons).

And coming from the other side: If it turns out that the brain is actually an analog computer without anything that can be rephrased as some form of sloppy noisy approximately-digital error correction, this would be incredibly important discovery, completely changing our understanding of theoretical computer science and complexity theory. P-vs-NP or the eventual creation of quantum computers would pale in comparison to the impact of discovering scalable analog computers.

Agree mostly, except for "error correction .. inherently digital"

For an example of an analogue error corrector, see https://en.wikipedia.org/wiki/Centrifugal_governor

PS. cool fact; "governor" has the same etymology as kubernetes.

Inference is typically much more power constrained, as it is often performed on a battery. For example in a mobile phone, or in an IoT sensor unit. This makes approximate computing for neural network accelerators an interesting field of research.

Where does the energy go in neural network workloads?

Wires.

To and from memory, in the memory dice, on the compute die, in the register files, etc.

Check out the paper "DNN Dataflow Choice is Overrated". And that's for the most compute bound cnns!

Edit: and if you think there's enough SNR to make analog "deep" processing in memory work, go make a quick billion dollars by expanding commodity memory with multi level. If you can add another level to flash you'll get rich quick.

>Analog computers making a comeback ? you never know.

The main advantage they're advertising for the analog parts is that you don't need an ADC or DAC. That's not helpful for computers, but it can be very helpful for specialized signal processing parts.

Pretty cool, I think the rub will be how well they can control the PN boundary and hence the switching thresholds.

The simpler NOR gate was pretty cool too, so their next step should be to build a RAM chip (either a 2 gate equivalent dynamic cell or 4 gate equivalent static cells) If they can do that, then they can show that the process can be controlled well enough for reliable gate fabrication.

Then the step after that might be mixed mode analog/digital circuit paths. Process control gets even harder when you're doing analog as non-linearity propagates and you can't ever get rid of it.

A typical zener[1] has a variance of >100mV for its breakdown voltage. The "easy" analog circuits in my radio need better than 40 dB of dynamic range which is more like 1 mV so 100 times better than a zener. I'll have to read up more on the device physics to see if getting that level of precision or better is really practical.

[1] http://www.vishay.com/docs/84830/plzseries.pdf

> A typical zener[1] has a variance of >100mV for its breakdown voltage.

My interpretation was that that was the point of the substrate biasing:

"A second tunnelling junction, represented by two horizontal lines in the device diagram, biases the device so that it is ‘on’ (but not saturated) when the tunnel terminal is open-circuit. While this represents a continuous current flow to ground during operation, tunnel current is typically only 2-5nA [...]"

The static power dissipation might be a problem, depending on its magnitude, and would only be exacerbated by the increased density. On the other hand, the increased density allows for lower latency relative to CMOS, and latency improvements are hard to come by.

These are insulated gate transistors so you don't need base current. It might not be too bad actually.

If it is Zener-ing, there is some base current, no?

The article says there is "some" static power requirement... that sounds like base current to me.

What's the likelyhood that Intel, TSMC or some other fab company already stumbled upon the process in r&d and binned (hehe) it due to some unforeseen difficulties making it not worth investing?

What is "plasma metal edge" and "wet edge metal"?

The article is a unique usage of these words in that order...

Edit: generally the article feels a bit like word salad for April fools (however, I only have an undergraduate EE knowledge of transistor design, so there's a lot I don't understand in there).

Edit 2: if it were a good chance to become a breakthrough tech, why is it missing deep VC level funding to get it to market? I know it's not software, but neither is it limited by FDA regulations!

It is how you etch the metal-device contact. Using liquid or plasma.

Plasma etch is more expensive and slower, but is easier to control.

> Edit 2:

Electronics is not in vogue with those people. Just like in computer science, the few breakthroughs that matter in last few decades went by nearly completely anonymous despite their enormous utility, but every cat video website gets... you know.

This looks interesting, but it's very early days. No mention of reliability, variation, interconnect (modern CMOS processes have 8-10 layers of interconnect). Certainly not taking on CMOS anytime soon.

Does the quantum tunneling have a lower limit on node size?

This is being developed it seems to keep a 1um fab competitive, but does it also apply to smaller nodes?

It’s got a terrible reputation on repeatability on a process. One reason tunnel diodes never went anywhere. They were expensive, tetchy and unreliable!

There was one big application for tunnel diodes: fast comparators. IIRC many classic Tek scopes use tunnel diode based comparator in their trigger circuitry.

On the other hand doing the same thing in some modern bipolar process is significantly cheaper and more reliable.

Another thing is that in such designs the tunnel diode looks like it does nothing. And that may have something to do with most engineers not using it.

Exactly. I actually have few ex Tektronix trigger tunnel diodes here[1]. Repairing the infernal scopes was a hobby of mine until I got fed up of it. By the mid-80s we had cheap ECL comparators which were much faster, required no bias calibration and lasted a lot longer.

[1] https://imgur.com/5ijmSh8

This is absolutely incredible, I can't wait to see what foundries adopt the process.

EEVblog (Dave) entered the chat

hope he makes a video about this development.

Is there a problem with charge, like in MOSFETs?

Is this what you are thinking of? "Bizen also does not suffer from CMOS’ electrostatic discharge (ESD) susceptibility and latch-up problems."

I bet it does suffer ESD issues. Even “SWR proof” RF BJTs are fragile. Anyway not that it matters really here even for CMOS as the ESD protection is just on the die lands. Most of the devices on the thing don’t have ESD protection on CMOS.

I think the question is about gate charge.

And I guess gate capacitance may cause signal-delays.

Not just delays. Being able to drive a transistor fast can be important for reducing power dissipation. That is, for switching one wants the transistor to spend the least amount of time in the non-saturated (linear) region where it acts as a resistor.

Judging by the process size quoted in the article, they won't be chasing speed, but rather low-cost devices.

Yes, that's what I was wondering about.

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