No. Unlike mainstream CPUs, for which sufficient information is publicly available to develop competitive compilers, FPGAs are closed systems. There is enough documentation to write the synthesis and map steps (which compile VHDL/Verilog/whatever to an architecture dependent netlist) and for the place step (which assigns instances from the netlist to blocks on the FPGA device). For the remaining steps (routing, static timing analysis, and bitstream generation), hardly any required documentation is available.

For a couple of small, outdated FPGAs, some of that information has been reverse-engineered and used for open source software, but I don't know how reliable, e.g., their static timing analysis is. I would never, ever use that for a non-hobby project.