Xilinx rolls out easier-to-use free FPGA programming tools | Hacker News Reader

Xilinx rolls out easier-to-use free FPGA programming tools

theregister.co.uk

14 pointsgballan10 comments

I remember reading Bunny Huang's book "hacking the xbox" and feeling so empowered to build projects with FGPAs. So I took two semesters of Verilog in University. However I have never been able to translate that knowledge into anything remotely useful.

TBH proprietary tooling this is just not the way to go. The FPGA space needs solution which works across FPGAs of different vendors.

Besides there are way better alternatives to VHDL and Verilog that I feel High level synthesis is kind of dead.

Which better alternatives to VHDL and Verilog do you mean?

Clash mainly. I have also heard amazing things about bluespec but I have never used it myself.

I just took a look at clash. HDL describes state in a very real way. Trying to represent stateful hardware using a functional language is just too complicated. I hate these toy examples of “look how easy an FIR filter is.” An FIR filter isn’t hard to write in Verilog to begin with. The real headache of Verilog is generate statements and multidimensional array indexing. And both of those problems are readily solved by System Verilog, System C, or any of the myriad of Verilog generators.

Your comment about clash and functional languages not handling state correctly are shortsighted. I have implemented real systems using Clash. The usability is simply leaps and bounds ahead of stuff like System Verilog and System C. The real headache of Verilog and the like is that it has little ability to abstract making you think that the real problem is stuff like multidimensional array indexing.

I'm not sure what you expect on a front page of a technology they have to show really simple toy examples and can't really dive in deeper. It's a front page... You can find myriad of more involved stuff if you would have googled for 5 seconds. For instance this https://clash-lang.org/blog/0001-matrix-multiplication/.

I guess my point is that Clash is just a high level language that transpiles to Verilog. There a plenty of languages that already do this. So your original claim that it is a Verilog or VHDL replacement isn’t accurate. We still use Verilog.

Companies have been autogenerating Verilog from high level languages for decades.

Just to be clear, I’m not trying to put down Clash. I disagree with your statement about it being an alternative to Verilog or VHDL. It’s like saying Java is dead because Scala exists.

Java and Scala are at about the same level of what you can do with both. Clash isn't really at the same level as VHDL or Verilog. You are right that it still compiles down to VHDL or Verilog but that doesn't mean anything. Haskell also compiles down to machine code. Does that mean you might as well write machine code? Of course not.

What's your point that there are other languages that compile down to Verilog? I have tried some of them and most of them try to shoehorn a software language into digital design which doesn't fit.

SystemVerilog and synthesizable SystemC, at least.

Reply on news.ycombinator.com