A computer built from NOR gates: inside the Apollo Guidance Computer | Hacker News Reader

A computer built from NOR gates: inside the Apollo Guidance Computer

righto.com

127 pointsmatt_d25 comments

If you like this kind of thing I suggest watching Ben Eater on YouTube or his website.

Ben explains and builds basic computers from components. It's more to see how things work like registers and memory addresses. It's a nice mix of electronics and computer science.

https://www.youtube.com/channel/UCS0N5baNlQWJCUrhCEo8WlA

https://eater.net/

Ben is a godsend. I remember having my mind blown by his 8-bit microcomputer series after years of wondering "okay, I know how to program, and I know about assembly, but....what's after that?"

When I ended up taking a MIPS class not too long after, it felt more like a recap of Ben's material than anything new.

Back when I was a CPU logic designer, I worked on two machines that used ECL logic, where the basic building-block gate was a 4-input OR/NOR (the gate produced both phases at output). I recall that on one of these machines, each logic card was supplied with well over 100A on the -4.5 supply, we had a space budget of 98 cards. But the tough limit to hit was cooling. For the entire CPU we had only a single 20 BTU-ton water chiller, and had to sneak everything in under the cooling limit.

I was one generation behind you. We had actual flip/flops and even small ROMs, made from something called CTL (complementary transistor logic) which was similar to ECL in its voltage and power requirements. But did not require water cooling, just banks of large squirrel cage fans.

> For the entire CPU we had only a single 20 BTU-ton water chiller

We'll probably get there soon again, this time for gaming PCs.

Was this at one of the mainframe manufacturers?

(https://en.wikipedia.org/wiki/BUNCH)

Control Data?

I was impressed to learn that when Margaret Hamilton programmed this machine, she wrote an interpreter, and coded the mission logic in the interpreted language. So, in a sense, it really was microcoded; but the microcode was what looks like the real instruction set, and the instructions actually used lived in ROM.

The Xerox Alto, which was used for the original Smalltalk in 1972, also worked much this way: It had 16 program counters, one of which pointed to a program for interpreting Alto instructions. Other program counters were for refreshing the screen, operating the disk, driving the laser printer, and moving network packets. An interrupt just changed which program counter instructions came from.

The Smalltalk runtime was another interpreter, interpreted by Alto (interpreted) instructions. People complained about how slow Altos were, no surprise.

I might have misremembered some of the details above. Corrections welcome.

The author of this article has a whole set of articles on the Xerox Alto (http://www.righto.com/search/label/alto). This one focuses on the microcode: http://www.righto.com/2016/09/xerox-alto-restoration-day-5-s...

The Interpreter was written by Charley Muntz, not Margaret. Margaret wrote a large chunk of the DSKY display routines and a lot of the alarm/abort logic.

Thank you for the correction.

Back in the 1990s, UC Berkeley's computer hardware quals exam used to require the test taker to design a microcoded RISC processor out of NAND gates, from the bottom up. It was kind of like Little Alchemy, once you created every kind of primitive gate you needed, you could assemble them to make larger and larger things. This included building latches, registers, static RAM, bottom to top. NOR is just NAND with 0's and 1's reversed.

NAND or NOR preference is due to the underlying transistor technology. NPN transistors (with electron majority carriers) tend to be stronger than PNP types (with hole majority carriers) at comparable sizes. In the beginning we had mostly bipolar processes, where we used NPN transistors in parallel to pull down the output and pull-ups were simply resistors. NOR gate was the natural configuration efficiency/cost wise. Later CMOS processes came along and we no longer use resistors for pull-ups (which tremendously reduces the quiescent current and makes CMOS perfect for digital logic). With CMOS it makes more sense to use the weaker PMOS (PNP) transistors in parallel for pull up and use the stronger NMOS (NPN) transistors in series for pull down and the natural configuration is the NAND gate.

Preference for NAND and negative logic (ie. active low) do not stem from early CMOS, but from TTL. TTL NAND is same structure as invertor, only with multiple emitters on the input transistor. And with TTL significant current flows only in the low state, typical TTL gate sees undriven input as logic 1.

By the way for CMOS, NOR is somewhat counter-intuitively still preferable as the two series connected PMOS pull-up transistors can be collapsed into one dual-gate PMOS, which leads to more desirable gate geometry.

This is the reason why CMOS CD4000 is NOR (and without looking it up I don't even know what is the P/N of 4000-series 2-input NAND), while TTL SN7400 is NAND.

On the other hand in modern CMOS processes and particularly in CMOS VLSI design this distinction is mostly moot.

That is basically the premise of the awesome Nand2Tetris[0] book/project.

[0] https://www.nand2tetris.org/

Edit: Just saw that it is even referenced[1] in the article itself.

[1] https://www.righto.com/2019/09/a-computer-built-from-nor-gat...

One of the classes at my university had a tradition of a guest lecturer coming in and give a two hour talk on “building a computer with magnets” at the beginning of the quarter to incoming freshmen. He’d go through pretty much the same things you mentioned, combining smaller components as he went into more complex ones, culminating in a computer that could do a full fetch-decode-execute cycle (whimsically, powered by the turning of a water wheel).

This is pretty much the approach I took a few months back after reading _But how do it Know?_ by J. Clark Scott, although I wrote it in software [1]

[1] https://medium.com/swlh/i-dont-know-how-cpus-work-so-i-simul...

How much time did you have for this exam? Building a complete processor starting from gates is not exactly a thirty minute exercise, even with a minimal instruction set & narrow datapath.

I recall having to do something similar for my "computer architecture" exam (in Italy) in very limited time (it was on paper during an oral examination), but I could get away with a very simple not-even-pipelining design.

NOR was used instead of NAND because the latter would've required a series connection of transistors, which changes the voltage levels needed and otherwise complicates the design.

NOR gate logic, like NAND and NOT/AND/OR gate logic, are functionally-complete.

Combinational logic examples:

- NOT gate -> N-input (N >= 1) NOR with all inputs tied together to the input

- N-input OR gate -> N-input NOR gate with a NOT gate at the output

- N-input AND gate -> N-input NOR gate with a NOT gate in front of each input

- Bonus - sequential logic: S-R latch -> 2x 2-input NOR gates with one each of their inputs tied to the other gate's output

should be N >= 2 because you can't really have 1-input NOR gate...?

A 1-input NOR gate is more commonly known as a NOT gate.

http://www.ibiblio.org/apollo/ has simulation information and a physical project built with 74LS...

Why three inputs?

Most certainly a compromise. More inputs amortizes more of the overhead (power pins, input pads etc), but too many wastes density.

A similar issues shows up in FPGA where four-input lookup tables (LUT4) were the sweet-spot for many generations but in the past few years LUT6 (and hybrids like the ALM ~ 2xLUT6) have taken over.

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