Arduino MKR Vidor 4000 – Arduino, Cyclone 10 FPGA, MiniPCI Express, MicroHDMI
arduino.cc
arduino.cc
Not sure what this is trying to be other than an eval board for 'also rans' in the FPGA and Cortex-M space. One of the reasons I like the Lattice FPGA boards like the Icebreaker[1] is that there is a complete open source tool chain for them. Seems like adding a processor to something like that might be an interesting place.
As far as I know, the bitstream for 15K/35K/50K Artix-7 is pretty much done, with Kintex-7 and Zynq devices being WIP [1]. I think there are gaps in support for the various hard blocks and PAR at higher layers of the toolchain, but the bitstream reverse engineering per se isn't a maybe-in-the-future thing.
There is no good business case for the smaller vendors to develop and maintain a full set of very complex software either.
And their "unsupported" tool is also used successfully today by rafts of actual hardware engineers, and it's still better than the free alternatives by leaps and bounds.
There are no plucky garage shops or "wise crowds" making FPGA tools that are even in the same galaxy as ISE or Vivado.
Symbiotic EDA comes to mind. However, I would argue they don't need to be great, just good.
I don't have a copy of Vivado to hand (I have an Altera dev board instead), but I can take PicoSoC with Yosys/nextpnr and have a bitstream in about a minute. If I try the same task in Quartus, that takes about five minutes. Producing a (relatively) inefficient bitstream actually speeds up the compile/run cycle in that scenario.
If the design meets timing, which is often decided by external factors, any extra time spend trying to make the design "better" is wasted time.
So it is more like a configurable microcontroller, rather than a fully programmable FPGA, at least that's my understanding.
Which I guess makes sense, given that FPGA programming isn't exactly n00b friendly from what I've gathered.
It can be OK. The first class most EE students take at my undergrad uni had a significant FPGA component.
https://forum.arduino.cc/index.php?topic=602341.0 (response #5 is useful)
Now it has its own article on HN:
https://news.ycombinator.com/item?id=21057511
Remember to upvote!
(Oh, and "You're welcome!" :-) <g>)
I've looked into some of Lattice's stuff, and some of their chips seem pretty capable for this, but as with all the other FPGA manufacturers, the toolchain is crazy proprietary. I'm not a huge fan of sinking my time into tooling I have no control over.
Can take Tensorflow models and convert them to Verilog. Tensorflow already has lots of tools to train quantized models, so all you need to do is convert them to hardware.
If you had a big enough Lattice FPGA you the open source Yosys toolchain, or use one of the Vendor proprietary toolchains for Altera/Xilinx.
[1] Disclaimer - I went to school with the creator of LeFlow.
It has inferior QoR compared to the closed toolchain.
FPGA manufacturers have pretty perverse incentives when it comes to filling your FPGA devices up with useless junk.
Not sure if this board will be wild success. Diligent has better boards with Xilinx Artix-7 for this price. Arrow MAX1000 is even more affordable. Intel MAX10 is a great device! Learning FPGA means always learning quirks of vendor’s IDE.
€62.90
I'm mainly interested in size and speed for this specific chip and speed grade.