TSMC: 3nm EUV Development Progress Going Well | Hacker News Reader

TSMC: 3nm EUV Development Progress Going Well

anandtech.com

135 pointshourislate63 comments

EUV is definitely solidly in the realm of magic for me. A spray of tin blasted with 2MW of lasers into a plasma to generate the “light” which is then bounced off of mirrors which barely qualify as mirrors to produce a focused beam to burn in features only a handful of atoms wide... 100,000kg of equipment. $100M per unit.

It’s mind boggling.

This is the first I've heard of EUV, so I don't have an informed opinion of it at all, but some quick googling shows that Intel will be using it for their 7nm process.

Does this mean that Intel's "7nm" should be considered roughly equivalent with TSMC's "3nm"? And who's typically considered to have the lead on fab tech nowadays?

No. And anyone but Intel.

Intel 7 nm ~= TSMC 5 nm.

TSMC is definitely in the lead; maybe Samsung is #2.

https://en.wikichip.org/wiki/7_nm_lithography_process

The leadership has definitely shifted to Taiwan. TSMC 7nm is roughly equivalently to intel 10nm. At leastTSMC first version of 7nm. But TSMC is now well in to ramping their 2nd/3rd iterations of 7nm. And ramping 5nm soon-ish, now this news on 3nm.And Intel has stumbled badly on 10nm, they are now years behind where they wanted to be. Intel are still launching new high end skus on 14nm through 2020. They are shipping 10nm in some volume, but with evident problems still on frequency binning and yield.

I would rank it probably as: 1) TSMC 2) Samsung 3) Intel

AMD now divested into Global Foundries used to be on there as well, but they're pretty much dead in the water at this point. Both AMD and Nvidia use TSMC now actually. It's kind of funny that Intel is the only remaining foundry within the United States at this point except for maybe Texas Instruments, which lets be honest, doesn't really count.

Global foundries still does plenty of production, most chip production doesn't occur at cutting edge nodes.

You're exactly right. There's a lot of money to be made outside of 3/7/10nm. I'm not sure why geeks get hooked on having the smallest/biggest or nothing and assuming anything else is failure

It's because it's immensely cool what humanity can continue to achieve.

>most chip production doesn't occur at cutting edge nodes

Of course, but the margins are much better on cutting-edge nodes. Being second-to-market on a node doesn't save you much on capital costs, but you have to compete harder on wafer pricing. TSMC have about 5x the revenues of GF and the gap is widening.

> Of course, but the margins are much better on cutting-edge nodes.

No, not anymore for at least a decade, and this is the very reason GloFo bailed out on the "Arms Race." Extreme capex with uncertain payback times looked very scary to their investors.

TSMC 7FF will only break even next year.

>TSMC 7FF will only break even next year.

I've no idea if that's true but assuming it is, then from next year it's pure profit and they are the big fish in a pond of 2 (or 3?) fish with no new fish in sight. People will be using this process for years and years to come. With so little competition at 7nm and the high barriers to entry (even over time) they can surely maintain their margins for much longer than at previous nodes. I'm not saying bailing wasn't the right decision for Global Foundries and the risk might be higher now, but so the rewards.

I don't think Texas Instruments deserves to be counted out. Their revenue last year was greater than Nvidia. Given that the margins on microcontrollers and DSPs are not nearly as large as on GPUs, they're shipping a lot of chips.

Granted I have no idea what their process node is, which they don't advertise anywhere presumably because people buying microcontrollers and DSPs do not really care about an arbitrary silicon feature size number. It's probably not cutting edge, but they're a big foundry regardless.

GlobalFoundaries is definitely not dead either. They even do 14nm which is hardly very outdated (and is probably the last practical node anyway).

ON Semiconductor has 700nm down to 180nm for hire in the US.

https://www.onsemi.com/PowerSolutions/content.do?id=18397

https://www.onsemi.com/PowerSolutions/content.do?id=16678

ST has been boasting about their new STM32G series as being their first 90nm product, though I doubt it'll start a nm race in the microcontroller world...

https://blog.st.com/stm32g0-mainstream-90-nm-mcu/

There are plenty of 40nm MCUs already

I see Renesas has some[1], got any pointers to some others? Would be interesting to compare specs.

[1]: https://www.renesas.com/jp/en/about/press-center/news/2018/n...

ESP32, gigadevices, some nuvotons

Correction, gigadevices are still at 55

Well there ya go. Been using the ESP32 for a while, yet blissfully ignorant of it being a 40nm device. Though I guess that explains how they can get all that SRAM in at that price point?

The word "foundry" refers specifically to a company that manufactures others' chip designs for them, such as TSMC. Intel discontinued it's foundry business AFAIK.

The more general word would be "fab", which is any semiconductor manufacturing facility.

Oh wow, I wasn't aware of that. Intel really has fallen quite low. I worry about it's future as AMD, Nvidia, and TSMC pull away at it from all sides.

> It's kind of funny that Intel is the only remaining foundry within the United States at this point

Samsung Austin is in Texas.

That sounds like saying two people will draw lines that have the same width because they use the same ink.

Intel doesn't have anything 7nm yet, there is nothing to consider in the first place.

They failed hard at their 10nm process, and are still struggling to recover from that.

TSMC is the the indisputable leader on fab technology at the moment

EUV is just one aspect of the process, and so far none of the lithographies are fully EUV anyhow (only using that on a few layers)... I'm not that well informed but I'd guess by 3nm it'd be fully EUV? Regardless; it's just one technique.

Just because a bike has a few carbon fiber spokes doesn't mean it's the same as another bike with a few carbon fiber spokes. The rest matters too, not least of which the other spokes ;-) and there are probably differences between carbon fiber spokes too!

Chips are built in layers, with the actual transistors being in the (lower) base layers and the wiring being the (upper) metal layers. The metal layers themselves form a stack with layers with thin wires at the bottom and layers with very wide wires at the top. These wide wires are used because they have less resistance and therefore allow faster and longer-range data transmission across the chip. They are wide enough that EUV won't be used there for a long time (if ever).

But even the base layers aren't all EUV yet, at least not in the first gen EUV-enabled processes, or is that a misunderstanding?

At least I thought DUV was still in use in combination with (not entirely replaced by) EUV.

Yes, that was precisely my point: a mix of EUV and DUV is used because the upper layers don't need EUV and DUV is cheaper and more mature.

Furthermore, it seems likely that the uppermost layers will never use EUV and that therefore a mix of EUV and DUV will always be used, indefinitely. This seems likely unless EUV surprisingly becomes much cheaper so that unifying on a single technology becomes worth it, or unless both EUV and DUV are replaced by something else entirely.

It's pretty mind boggling indeed. Back in 2005 I did an internship with one of the two manufacturers of lithography lensing systems, in their R&D. It was very interesting and certainly showed me that my physics studies weren't really teaching me optics at all.

Weird anecdotes: the people working on EUV didn't believe in it at all. It was a big joke to them. But the roadmaps were showing it... not in 2019. The mirrors were being polished by hand. Robotic tools are more accurate, but the inaccuracies they produce are aligned, creating optically meaningful patterns. So instead they had two guys with PhDs in metallurgy polishing mirrors. The all important simulations of lensing systems were done with classical optics and a ton of FORTRAN. Certainly throwing in some phenomenology around effects that are ultimately quantum effects, but no out there quantum optics or anything of the sort. This was 2005 though. The weight of the lenses itself changed their optical properties enough that we would measure the stresses induced by their weight and the impact on optical properties so we could include that in the system end to end error budget.

What sort of optics did you feel weren't covered by your physics courses?

It was a half semester only in an early, first or second year experimental course. It felt mostly like an advanced high school course that was rigorous on the math. For example the birefringence I mentioned in my previous comment wasn't even mentioned. It also want treated from a theoretically engaging/pleasing angle. It was a course that had to be taught rather than being loved of you know what I mean?

Are there any photos of these manufacturing machines? They sound amazing.

Try searching for EUV and ASML, that's the largest manufacturer of these machines.

Marketing video that has a bunch of nonsense and a few interesting shots: https://www.youtube.com/watch?v=jL3TYXr52BY

I am a little bit curious...if ASML makes the machines, why is TSMC taking credit for 3nm development? Or are the machines not fully developed out of the box and need more work to achieve different nodes?

My guess is the following: ASML produces the lithography machines, and TSMC/Samsung/<chipmaker> uses them in mass production. What I hear from the Dutch news is that the development process is very much a cooperation between different companies. What works in ASMLs lab will likely need a lot of tweaking before it can be used in mass production.

That's exactly right. This is as much science as it's engineering!

Here's a talk that's pretty mind-boggling, too:

Indistinguishable From Magic: Manufacturing Modern Computer Chips

https://www.youtube.com/watch?v=NGFhc8R_uO4

It is a very large ritual that requires unique artifacts for the sole purpose of engraving small crystals which are then socketed into larger edifices and imbued with the spells of many wizards before they are distributed by territorial guilds to common man, in exchange for a recurring obol. Entire fiefdoms have been erected by merchants of these artifacts of power. But as we come to depend on their miracles more and more there are concerns that The Enemy could dispel or corrupt them... well... let's leave it at that, entire schools of warding, counter-warding, arithmancy etc. etc. are dedicated to these topics, more than we could cover here.

Oh, and beware of charlatans who want to sell you so-called artificial soulstones, they are awfully common in these halls. The gems are tools made by man to imitate the divine spark, but they can never rival or become the genuine article.

I guess 3nm is just marketing, but I’d be interested in better understanding the feature sizes here and in current processes.

From what I can tell, in their current 5nm process the smallest features are on the order of 30nm? Is that correct? [1] I guess what I’d really like to see is some structures and annotation showing feature sizes. These rarely seem to be shown.

[1] https://en.wikipedia.org/wiki/5_nanometer

Transistor (FINFET) width should be around 7nm for the 7nm process (https://en.wikichip.org/wiki/7_nm_lithography_process) but you are right that transistor pitch isn't scaling nearly as fast so transistor density is not going up as fast. Cost per transistor was actually flat (maybe even going up) at the 7nm node.

What's perhaps even worse is that metal pitch doesn't scale as fast. As a consequence, the ratio of wiring space per transistor has been decreasing for a couple of nodes now, which makes wiring much more difficult and makes it more difficult to use all the transistor area effectively. Basically, designs more frequently have to reduce their density of useful transistors in order to be able to lay down the wiring connections.

The number of metal layers can be increased to fight back against this effect somewhat, but you still need space for vias to go through the lowest metal layers, and with design rules getting more complex placing those vias is itself getting tougher (though obviously EUV for metal layers helps there because it allows the design rules to become a bit more relaxed).

So it turns out there aren't any 7nm EUV in high volume ( comparatively speaking ) shipment from TSMC as originally expected. While this isn't confirmed, I would assume Apple to have make a bigger announcement in Keynote if they were using 7nm EUV, since they only mentioned 2nd-Generation 7nm, this is likely an improved version of 7nm DUV, aka N7P ( 2nd Generation 7nm is also an Semi Official Term TSMC uses to describe N7P, while specially mentioning EUV when it is involved ).

The question we have now, would Apple A14 be 7nm EUV, or would it be 5nm? If it is 5nm as the original cadence suggest, then we could expect 3nm EUV A16 in 2022.

And Intel doesn't plan to ship their 7nm EUV till late 2021, in a volume likely much smaller than anything currently Apple ships.

What will we do below 3 nm?

Presumably 2 nm.

How many silicon atoms is that?

A silicon atom is 0.2nm.

The funny thing is, it doesn't matter. "2nm" is just marketing; nothing about it is actually 2nm in size. But that's okay, because that was true at 7nm and 14nm and even at 28nm.

So what 2nm really means is "better than 3nm".

Why do we all go along with this charade? It’s so silly and unscientific. Why can’t we just call the things correctly?

It is the same reason why we use millimeters of steel as a measurement of the armor performance of tanks even though they use composites of different materials.

Because it is easier to compare two numbers even if they are meaningless in reality.

It would be better to stay quiet instead of comparing things incorrectly.

there is no correct single number to use

SRAM density is a pretty good single meaningful number

Isn't the smallest trace/spacing 2nm? Most is larger but 2nm is possible for some traces/spaces.

As many as you want.

Nothing, we will stay at 3 nm.

Carbon nanotubes, graphene, photonic chips, more involved silicon designs.

There's no shortage of ideas, just uncertain ROIs.

The 7-5nm was said to be so much a barrier before. I'm sure this will unleash a ton of capital and brains to keep digging.

ps: I heard spintronics and neutronics caught some wind on paper

There is a new exciting paper about DNA computers as well.

https://www.chemistryworld.com/news/leap-forward-for-molecul...

Hah, Woods of course. Two years ago a previous colleague of him hosted a talk in Paris. I got a peek of the work it was truly staggering. But the guy told me they were too instable at scale so far. Sounds like a solid hint at the future though.

ps: do you work in this field ?

Not at all, just an interested layperson (I'm in 'normal' IT). My partner studies evolutionary genetics (or something like that), so we talk frequently about biology. There is another DNA computing paper that was very interesting published earlier this year by another group, but I can't find it now. I think it was in Nature.

Actually spintronics unlike others is ready to come to mainstream, through MRAM.

Not a good week for intel

One day, maybe, but not soon.

It's great that we can have dream machines at ridiculously low prices, but these machines are valuable enough that we'd buy them at 2x or 3x the price, easily. There'll be a whole lot of grumbling and complaining, as always. But people have grumbled and complain since the iPhone 1 and every year there after --- and they've been MASSIVELY wrong about the value of these devices compared to their costs, and so, just how desirable they are.

At the end of the day, are you not willing to pay $5K extra from a car that's REALLY self-driving and ultra-safe? Would you not pay $3K for something like your phone, only with enough performance to translate any text or words you hear, and to behave as intelligently as a human secretary?

Think of the billions in electricity saved each new size reduction, for data centers and even the general pop doing the same thing as ever with less current, or more for the same cost.

I watch 4k videos a lot, imagine the cost of rendering that 20 years ago.

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