16-bit RISC-V processor made with carbon nanotubes | Hacker News Reader

16-bit RISC-V processor made with carbon nanotubes

arstechnica.com

135 pointsTomte35 comments

For those of us wondering what they meant by 16-bit RISC-V (as there isn't a 16-bit RISC-V ISA), it's just 32-bit RISC-V instructions operating on 16-bit data and addresses.

Sort of what the MC68008 was ages ago: 32 bit internal architecture but reduced external data and address buses so the chip could be used to build simpler/cheaper systems.

I think it's more like a 16-bit internal architecture and buses - so PDP-11 sized, add a rudimentary base and bounds swapping MMU and you have enough to run unix

RetroBSD would probably be a good starting point for anybody interested in porting a unix to this device. It's based on 2.11BSD (a backport of 4.3BSD features to the PDP-11)

I've looked into porting it to the Nintendo DS. It should be doable, but I haven't had the time to commit to it. Maybe I'll give it another look this weekend.

Or the 8088, 16 bits internally, but external buses (memory, port i/o) only 8 bits wide?

MC68008 was internally 16-bit. 16-bit "add.w d0, d1" takes 4 clock cycles and 32-bit "add.l d0, d1" takes 8.

32-bit internal architecture here meaning 32-bit registers, and a greater than 16-bit address space (yeah it's not full 32-bit, but neither read the full 68000).

68000 was a 32-bit ISA, but with 16-bit internals, mainly meaning ALU. 32-bit register file, flat 32-bit address registers (pointers). Moving data with move.l and move.w between registers was both 4 clock cycles. I wrote a ton of assembler on 68k back in the days and absolutely loved the large orthogonal register set and useful addressing modes. Going to x86 was rather painful after that. :-)

Some ways 32-bit, but 16-bit level performance.

I think in the end you can call it either way.

But like, a z80 had a 4 bit ALU and internal datapath, but I don't see anyone calling it a 4 bit architecture.

Now that you mention, z80 always felt so 4-bittish... ;-)

Haha, ok, fair enough. : )

No, there is a 16-bit version https://content.riscv.org/wp-content/uploads/2017/05/riscv-s... See chapter 12, “C” Standard Extension for Compressed Instructions

> This chapter describes the current draft proposal for the RISC-V standard compressed instruction set extension, named “C”, which reduces static and dynamic code size by adding short 16-bit instruction encodings for common operations.

The RISC-V compressed instructions are more a shorthand for some commonly used 32-bit instructions than a 16-bit ISA that stands on its own: the compressed instructions lack a number of essential operations that make it impractical to only use compressed instructions

This is in contrast to, say, the ARM Thumb instructions, where you can can have entirely libraries that use 16-bit instruction without ever needing a 32-bit one.

That's not what this is. That's just shorter versions of several common instructions to increase code density, not a 16-bit ISA.

Can someone ELI5 what the advantage a CNT based chip would be? Is it more energy efficient, or can they operate at a higher frequency?

Apparently faster and lower power, so a boon for mobile devices, data centres etc - plus a net positive if all computation is performed on them in energy consumption globally.

It doesn't appear that they would be any more environmentally friendly to create in the first place as silicon though.

They have much better carrier mobility than silicon has. We can keep reducing power/operation by shrinking transistors but it looks like if we're every going to increase processor frequencies against we'll need to do a substrate switch like this. And we can't keep shrinking silicon transistors forever, anyways.

We want to make transistors ever smaller to increase their energy efficiency and fit more of them on a chip. Scaling down transistors made of materials like silicon hits limits, as the distances become so small that electrons can leak through the materials.

In a field effect transistor (FET), you have a channel and a gate. The channel is a bit like a bridge which can be raised and lowered as ships travel underneath. Ideally, electrons shouldn't be able to flow between the channel and the gate (falling off the bridge), and depending on the voltage at the gate (position of the ship), the channel should range in resistance between zero (completely open; transistor is on) and infinity (completely closed; transistor is off).

In a CNTFET, the channel is replaced with a carbon nanotube. The nanotube channel is very good at keeping the current carriers (electrons) inside, and so leakage is small. Additionally, nanotubes are very good at carrying current. To use the bridge analogy, the CNTFET has a bridge that is very wide, and so allows lots of people across, and has high walls such that the people don't fall in the water or onto the ship.

Not quite the rod logic [0] processor I expected from the headline, but pretty cool!

[0] https://youtu.be/ORjyXcLDd9M?t=1536

Rod logic is super cool! Wish more people were looking into it!

The problem is you need a gain of greater than 1 for a sequence of elements otherwise the noise will eventually swamp the signal and lead to an ambiguous or incorrect result.

Can't you use some distributed amplifier principles to increase gain?

Awesome link! Thanks!

A creative way of getting around the low transistor yield that nanotubes are currently stuck with.

This is a stunt - but it's a pretty cool stunt

A link to the paper would be nice. Unfortunately nature.com is paywalled. Does anyone know what open source design they modified? I'm guessing PicoRV32.

sci-hub.se/10.1038/s41586-019-1493-8

Nice! This should really be the article link in my opinion.

Anyway I was wrong about the design. It looks like they implemented their own very simple finite state machine, but did use Clifford Wolfe's riscv-formal to specify it: https://github.com/SymbioticEDA/riscv-formal

A processor made out of tiny resistors?

Don't CNTs have some semiconductor properties?

How does that work? Wouldn't it be a low-efficiency one due to the higher material resistance?

Your info on CNTs are a few years out of date. There are some really remarkable experimental results that go beyond what the theory predicts.

Thanks. I read up on it and found:

    The electrical resistance problem

    In October of last year an IBM-led team of researchers reported a solution to the electrical resistance problem. In a typical configuration metal contacts are attached to the top or the sides of the CNT. The team from IBM placed the contacts at the ends of the nanotube. They also joined the nanotube to the metallic components of the integrated circuit with a molybdenum-based carbide.

    Intel current top-of-the-line chips operate at a 14 nm scale and Intel plans to introduce 10 nm chips in 2017. The team from IBM built a CNT transistor that showed no increase in electrical resistance with contact lengths from 300 nm to less than 10 nm.

https://www.forbes.com/sites/kevinmurnane/2016/09/08/carbon-...

Please quote properly, like this:

> The electrical resistance problem

> In October of last year an IBM-led team of researchers reported a solution to the electrical resistance problem. In a typical configuration metal contacts are attached to the top or the sides of the CNT. The team from IBM placed the contacts at the ends of the nanotube. They also joined the nanotube to the metallic components of the integrated circuit with a molybdenum-based carbide.

> Intel current top-of-the-line chips operate at a 14 nm scale and Intel plans to introduce 10 nm chips in 2017. The team from IBM built a CNT transistor that showed no increase in electrical resistance with contact lengths from 300 nm to less than 10 nm.

Your quote is unreadable on mobile, and annoying on desktop because of scrolling.

That's one way of looking at field-effect transistors. A chip is a collection of channels with resistances controlled by each other.

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