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Comment by chx | Hacker News Reader

Chiplets is what gives AMD an absolutely brutal advantage. Their high end chips do not need expensive large dies -- just a few small ones. Yields are much better. And they can bin each chiplet separately. Oh and they don't spend the expensive top notch process on the I/O part of the CPU either. Intel might be hard pressed to catch up to this -- sure the 7nm EUV process in two years and a bit will very likely be a serious jump in IPC but if you are comparing similarly priced server CPUs then even that is very likely to be simply not enough due to this chiplet strategy. For the foreseeable future, inertia alone is the only reason for anyone to buy an Intel server chip.

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So the chiplet strategy is clearly paying dividends for AMD but I'm curious as to what has changed to have allowed this idea to be so effective? It's not like the concept of multi-die CPUs is new, Intel even implemented this on their legendary Q6600 CPU which was basically 2 Core 2 Duo dies on a single chip. The issue with the approach used with the Q6600 was that communication across cores on separate dies was orders of magnitude slower than communication across the cores sharing a die. Is AMD's success down to recent advancements in brand prediction and core scheduling optimization?

> The issue with the approach used with the Q6600 was that communication across cores on separate dies was orders of magnitude slower than communication across the cores sharing a die. Is AMD's success down to recent advancements in brand prediction and core scheduling optimization?

The biggest problem with the Q6600 is that it was a big hack to communicate over the frontside bus, something designed for nice slow memory access that didn't have the bandwidth or latency for inter-core communication.

Infinity fabric, on the other hand, is good enough that on Zen 2 they didn't even bother to directly connect the two CCX that share a die.

But once they do get on the chiplet train properly, their EMIB technology means they only need a small 'bridge' piece of silicon to connect their chiplets. In contrast to what TSMC offer where all the chiplets need to sit within a large silicon interposer. This is more expensive and it limits the size of the chip you can produce (as there is a limit to the interposer size). They also announced that Foveros stacking thing and now co-EMIB too; on paper Intel's new packaging tech looks like it could really help them. They just need to make use of it.

Some chiplets don't need an interposer or EMIB (we used to call this MCM back in the day but whatever).

When one of the chiplets is responsible for IO and the others all need to talk to it, like AMD are doing, they do. I guess you could go down through the package and back up again like the olden days if you wanted a much worse solution.

Please look at an AMD processor before digging yourself deeper.

Intel announced a 56-core server CPU (presumably purely to try to keep up with AMD), which is just two 14nm 28-core dies “glued” together like Zen 1. But AMD clearly has an lead on getting this to market and optimising it into their current chiplets.

Intel has had a 56-core Xeon for a while, but there's been no essentially no interest from OEMs.

I don't think you can even get it outside of custom-built HPC machines.

The dual-die 56-core CPU isn't socketed; it's a massive BGA-soldered package.

The craziest thing about that 56-core CPU is its 400 watt TDP. Meanwhile 64-core Zen2 EPYCs top out at 225 watts.

Not the rumored 50k price tag for the -M variant that doesn't have max memory artificially limited?

I had no idea. That's... uh... why?

I guess part of this nonsense is the consolidation of cloud vendors. Intel is selling CPUs the way IBM sold mainframes in the 1960s.

If an uncrippled 28-core is $17K then putting two of those in one package is going to be over $35K.

Unlocking the memory capacity is a flat fee regardless of how many cores, so I think a better comparison price for the overcosting is $20k locked / $28k unlocked.

Back in 2007 at Microsoft I saw an 80-core Intel prototype. Didn’t really do much of anything, and there was only 1 of them, but it’s interesting seeing some of these old research projects come to fruition

that would be https://en.wikipedia.org/wiki/Teraflops_Research_Chip , looks like Intels take on Transputer

Thank you!

> Intel might be hard pressed to catch up to this

We were constantly saying this about AMD until Zen, and Zen is largely credited to Jim Keller. Where did Jim Keller go after Zen? Intel. I'm lowkey afraid that AMD will run out of steam after one or two gens and Intel+Keller will have just finished developing an insane architecture that brings us right back to the pre-Zen era.

It's a cycle we've seen before. Just enjoy the ride and take the benefit while it's there. Hopefully things are different this time, but many of us remember when AMD beat Intel to 1GHz and also the major win that was amd64 and the overclocking madness that came with Barton. This industry is cyclical in nature. I am an AMD fanboi from the K6-2 days, so I am a restrained optimist about the current wins.

> This industry is cyclical in nature.

I mis-read it as "cynical in nature", and it still fits. May the best process win.

Well that's how competition works.

I'd really like that despite Intel being in the driver's seat again - because I honestly don't see where single core performance is going to come from in the future. IPC increased because the CPUs used the inherent possible parallelism in normal code where often calculations don't depend on the value of the previous calculation. But now it seems to me like we're pretty much at the limit of that, adding more integer units/prefetchers/etc. isn't going to give us the growth we're used to. Cache is something with a decent amount of potential, but once that is gone, what are they going to do?

People who know these things have said that Zen was principally designed by a different individual, not Keller. I'm trying to find the link/who that person is.

Mike Clark (~tech lead) and Suzanne Plummer (~engineering group lead) are usually mentioned as the most important people.

Mike Clark. I have no inside information but the rumor I have read is that Keller was mostly responsible for the cancelled AMD ARM effort while Clark did Zen. Clark is explicitly credited as the architect/principal designer for Zen 2.

>Where did Jim Keller go after Zen? Intel.

He didn't went straight to Intel, You missed Tesla in between. And anything he is doing will be 2022+ at the earliest. Intel already has a roadmap of Chips that were delayed by Fabs, and that is at least up to 2022 / 2023.

I am pretty sure AMD has many competent people too. And as far as I could tell, I don't ever see engineering talent as a problem in any big tech companies. There are lots of insanely great engineers from Microsoft and even Oracle that most have not heard of, but most of the talents are hampered by cooperate politics and culture. And so far AMD seems to have a far better culture under Dr Lisa Su than Intel.

Is it the future of SoCs?

Definitely. Intel has said they're going chiplet with some talk about 3D chips too.

https://www.anandtech.com/show/14211/intels-interconnected-f...

Hotchips is full of chiplet talk. TSMC specifically calls out AMD, Xilinx, and Nvidia when talking about chiplets.

https://www.anandtech.com/show/14770/hot-chips-31-keynote-da...

Nvidia's Hotchips highlight is an AI accelerator with 36 chiplets on board (and interestingly, with a RISC-V controller -- probably the one they've been putting in their graphics cards).

https://www.anandtech.com/show/14767/hot-chips-31-live-blogs...

A chip can't bin faster than its slowest core. Getting 28 cores that run at top speed is almost impossible (even with Intel's super-stable 14nm and many chip design iterations optimized for the process). In contrast, getting 8 cores at a high speed happens much more often.

Likewise, a given manufacturing process is going to have an average of N errors per wafer. Duplication of parts of the chip can help, but they increase cost and some parts simply aren't economical to duplicate. If the error is in cache, you can probably laser off a cache block and move on. If the error is in the ALU, you probably aren't as lucky and will have to laser off an entire core (worse errors may even cut out an entire group of cores). A huge 28-core chip has a very high probability of an error meaning that you probably have a bunch of 26-27 core chips, but far fewer 28-core chips.

What is the chances of finding that magic chip with 28 defect-free cores where all of them also run at high-speed? This is one reason why Intel has so many SKUs. AMD also sells the same chip to both consumer and server, so they can take the best of the best and ship them to servers. If there's a defective core or two, laser them out and sell one of those 12-core desktop parts. If it's missing a core and doesn't clock high enough, sell it as a 6-core 3-series chip.

The ability to split fab nodes is also huge. Half of the new Zen 2 chip is 14nm. If they had to make that on 7nm as well, their supply would be halved and prices would go up substantially due to increased chip cost and decreased chip supply. If an interposer is needed, it can be even older (I think AMD used a 65nm for their Fury HBM interposer though something even older like 180nm would probably work just fine for wire-only interposers).

> A chip can't bin faster than its slowest core. Getting 28 cores that run at top speed is almost impossible

Of note here is that Intel tried to identify which cores on a die could run fastest so that low thread count workloads could use only the best cores on the chip, but the software side was a disaster and they have pretty much given up on the concept.

> AMD also sells the same chip to both consumer and server, so they can take the best of the best and ship them to servers.

They may also be sending the most efficient chiplets to the server parts that have so many chiplets on each package, while keeping some of the fastest chiplets for the consumer parts. There's really not much precedent in recent generations for having one piece of silicon span such a wide range of products.

A chip can't bin faster than its slowest core.

Intel and AMD recently started binning individual cores, although I don't think it has hit Xeon yet.

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