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Comment by blihp | Hacker News Reader

I can't see why it would. This would have mattered 20 years ago when there weren't more compelling ISA's out there. But that's not today's world: ARM is fairly ubiquitous and dirt cheap while RISC-V is a promising and open source up-and-comer. This seems like a relatively non-event (or worse: confirming that it's effectively a dying/dead platform) unless one has a significant investment in Power.

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I tend to agree, I think if IBM were to release some core designs to go with it then they could potentially spur something interesting.

I really see it two ways, the fact that Talos has real hardware that isn't priced up in the stratosphere (it's not cheap, but it's not insane) and then the ISA being opened. Those are giant steps for a company like IBM. At the same time, as big as those steps are for IBM, they seem like pretty small steps in terms of taking on the world with this stuff.

Throw in something like the full G5 design? We might be talking about something different.

They are more than willing to hand out old designs to university groups (you just have to ask nicely). In fact someone in our group spend his PhD developing a custom embedded Power processor in 65nm just to be told that when he was hired by IBM (whether he would have gotten the job is a different question of course).

Why does RISC-V being "promising" and an "up-and-comer" make it more compelling than an ISA that been around for a long time?

It already has a small and growing ecosystem. I agree there are no RISC-V barn burners but there are already more people with RISC-V design experience than there are for POWER.

I think all the major non-IBM POWER folks are at Apple these days and you know which architecture they are working on!

Having observed both sides of the industry first hand, I don't agree with that statement at all. Without going into debates on relative merit, RISC-V does its development in public while IBM until very recently has done it all behind closed tightly sealed doors. This might be giving a slightly unfair comparison on size of teams from a public perspective.

The IBM folks really, REALLY understand how to design a secure core and chip, plus the decades learning how to make a fast and relatively efficient core. RISC-V is simply in a far more nascent state, trying to push it to POWER9 performance (let alone AMD performance) is like saying a toddler just learning to walk will win a 10k marathon tomorrow. Eventually that may happen, but not in one day, more like 20 years. ;). And when you start chasing performance, who is doing the actual hard, tedious work of verification and making sure security flaws aren't being accidentally introduced into the implementation?

POWER is interesting to me because we get mature tooling on a proven ISA that can be built and run on high performance chips today. No more cross compiling, no more pure emulation required to do soft core work. That in and of itself is huge in the embedded space, and honestly I'd love to see the experimental and interesting cores currently decoding RISC-V ported to decode ppc64 -- all the sudden real comparisons on performance etc. for identical binaries become possible, allowing proper comparison of core design ideas under real world loading. No more guessing and having to take on pure faith that the performance difference is down to ISA or compiler performance -- either your core is faster / more efficient on the sane binary, or it's not!

Oh I don’t disagree with what you wrote except on one crucial point. Certainly agree that RISC-V is still in its baby shoes.

But IBM’s announcement is simply the ISA itself being open sourced (with some patent IP). Apart from an FPGA soft core there’s no RTL/VHDL. If you want to make silicon you’ll be starting basically from scratch.

Sure. While I would also like to see a real hard core or three released, here's my frame challenge:

What if the existing RISC-V and other academic cores are already good enough for a lot of people? The instruction decoder is a relatively small part of the CPU, swap that out and you suddenly get new SoCs that can run the existing POWER software base (that means proven toolchains, vector accelerated applications, etc.). Right now RISC-V doesn't even have vector instructions per se; adding all that support to the entire tooling seems like a lot of effort for not much gain when you can simply implement VSX in the hardware and use the existing tooling for it.

I keep hearing the open RISC-V cores are going to be very fast very soon. If that's true, how would an IBM provided core help versus an instruction decoder swap on one of those and some tuning?

It's more compelling because a number of research groups and companies are investing in designing and releasing hardware based on it. It has mindshare in the space that Power does not and is not likely to have.

Just opening the ISA doesn't mean that new players can start spitting out processors based on it tomorrow or even next year. And why would they want to? Power was never in remotely the same position that x86 is/was re: binary compatibility so being able to say 'Power compatible' doesn't carry much weight. An ISA which has been a minority player but around for a long time is more likely a liability than an asset.

For RISC-V to be a more compelling option than Power, it would need to be an option first, but if I need to buy a CPU today, I can't buy a RISC-V one.

I can, however, buy a wide range of PowerPC CPUs, for a wide range of applications. From embedded applications, like routers, to laptops, desktops, workstations, high-end servers, up to super-computer class CPUs.

Except neither of those are in the same performance ballpark as Intel, while Power ISA is.

I might be misunderstanding you, but performance isn't in the ISA, it's in the implementation. In fact, the x86 ISA is the best example for this: It's really difficult to get competitive performance out of an ISA designed in the 70s, yet billions upon billions of USD in R&D and optimization make it work.

The ISA matters, otherwise we wouldn't care about SIMD. If your ISA is missing SIMD functionality, then it doesn't matter how good your implementation is, it will be slower than an implementation of an ISA that supports SIMD when it comes to anything that can leverage SIMD.

Fujitsu begs to disagree:

https://www.theregister.co.uk/2018/08/22/fujitsu_post_k_a64f...

Fujitsu had already built SuperSPARC-based supercomputers, and Oracle recently ported their Red Hat clone to AArch64 (no legacy 32-bit or Thumb) and produced an ISO for the PI-3.

I won't dispute SPARC (Fujitsu has done some impressive work on it), but the post was for ARM and RISC-V.

The link I posted was Fujitsu's new ARM server, which bundles 32GB of RAM and over 30 cores on a single die. These are deployed in dual-socket blades attached to the "tofu" routing that they scavenged from their SPARC supercomputer.

Fujitsu is saying that their ARM implementation is the fastest server processor available, ahead of Intel.

I don't know why you compare processor implementations and then talk as if that generalizes to all processor implementations of a given ISA. Intel Atom chips definitively aren't in the same performance ballpark as POWER9.

I mean it should be obvious. The ISA does not dictate memory performance, micro architecture, clock frequencies, manufacturing processes, number of cores, maximum allowed power consumption, etc. All of those affect performance but are independent of the ISA.

Don't forget that MIPS also open sourced their ISA earlier this year as well.

Sort of. From what I've read, they "open sourced" their ISA in only a very weak sense of what it means to be "open source". Apparently there are a ton of restrictions on what you can do with their ISA even now.

Yes -- the target for POWER is basically competition with AMD Rome and Intel Cascade Lake and you need to have extremely deep pockets to compete there.

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