Specifically, the talk mentions that the 6502 was pipelined and could do many instructions in 2 clock cycles, while the Z80 needed at least 4.
This translates to 2x the speed at the same clock rate.
This translates to 2x the speed at the same clock rate.
For example the instructions NOP(or CLI, STI, INX etc), 1 byte, 2 cycles. 1 cycle for fetching the instruction and one for executing the fetched instruction.
LDA addr,x seems to be pipelined a bit though. It's "AD lo hi" in memory and takes 4 cycles unless lo+x > 255, then it takes 5 cycles. The lo+x calculation seems to occur while hi is being read.
I am restoring a 65c02-based //e clone, so, I may be able to properly measure instruction timings, but I won't hold my breath.
Sounds like a fun project.