What Is RISC? (1993)
danluu.com
danluu.com
However, this is a historical article... written at the time when the RISC vs CISC debate was actually a relevant discussion. That is how I think RISC vs CISC should be treated: as an ancient flamewar originating in the 1980s and 1990s about the architectures of that time.
Today: ARM, Power9, RISC-V, and x86 are all marching towards the same Out-of-Order, deeply pipelined, branch-predicted SIMD-accelerated load/store architectures with hidden reordering registers and multiple execution ports with 64-byte coherent caches implementing MESI-based messaging targeting Acquire/Release semantics over SMT Multithreading. The architecture wars are dead. All CPUs today have virtually the same architecture.
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RISC vs CISC harkens back to the days before the "best architecture" was known and discussions were about trying to discover the best CPU architecture. This (historical) article is great because it shows the way of thinking of the time... and provides a historical snapshot of the discussion (and evolution) towards today's architecture.
EDIT: Today, we can look back at the time and see that the "RISC advantage" was "easy compiler algorithms" to understand dependency-cutting, and how the CPU can use OoO execution (with assistance with dependency cutting from the compiler) to achieve high performance. To get these features on the x86, Intel translated x86 opcodes into a load/store microcode, an architecture that probably couldn't have been foreseen before the release of the Pentium-Pro.
RISC isn't the "best architecture" in context. CISC designs stem from days when CPUs were extremely transistor-limited:
* They might have only one ALU, and need to multiplex it cyclewise between, say, the IP increment and instruction operation. Or it might be half width and they need to multiplex it timewise to complete an operation.
* They might have only a few kb of SRAM to store code, so code density matters more and pipelined load/store architectures with all their orthogonal operations are too expensive.
* Likewise they might choose a two-operand instruction encoding to better compact code.
* They might not be able to dedicate transistors to a huge register store to cache all those loaded values and need a way to cheaply operate directly on memory to avoid extra spill/fills.
Basically it's easy to look back on RISC as the "obvious" way to get a CPU to be able to use all its diverse hardware more reliably by pipelining operations so nothing is ever idle. But in order for that to be a requirement you have to have all that diverse hardware. CISC ISAs were designed for architectures where that wasn't even an option.
> Out-of-Order, deeply pipelined, branch-predicted SIMD-accelerated load/store architectures with hidden reordering registers and multiple execution ports with 64-byte coherent caches implementing MESI-based messaging targeting Acquire/Release semantics over SMT Multithreading.
In short: Intel Skylake: https://en.wikichip.org/w/images/e/ee/skylake_server_block_d...
Which is pretty darn similar to say: https://en.wikichip.org/w/images/5/57/cortex-a76_block_diagr...
Arm Cortex-A76 is smaller because its designed for cellphones. But you can see how the overall CPU design principles are nearly identical to what Intel Skylake is doing. There was a time when ARM and Intel CPUs were extremely different: thus the RISC vs CISC debate. But its not the 90s anymore: today's architectures are extremely similar.
A lot of these features are being shared between all designs today.
The hard part is that some of these concepts are RISC (out-of-order, load/store, and deep pipelines). Some are CISC (SIMD-instructions and other hardware acceleration instructions, like hardware level AES or RDRAND instructions). Some are hybrids. RISC chips were traditionally multithreaded with relaxed atomics or maybe consume-release semantics. CISC chips were strongly ordered. Acquire-release semantics meets in the middle: stronger than consume-release, weaker than strongly ordered.
Finally, some tidbits are just happy accidents. DDR4, LPDDR4, GDDR5, GDDR6, HBM, and HBM2 RAM all work on 64-byte chunks (typically burst-length 8). So all modern chips work on 64-byte transactions with RAM. Neither a CISC nor RISC concept, its just everybody cooperating with the same cache-line size due to how memory works today.
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If you want to call it a "RISCy-CISC" or a "CISCy-RISC", maybe that will work. Modern architecture is a hybrid of concepts, taking the best (or blending the best features) from previous debates in history.
The important parts of history, is the discussion. The realization for why certain features were good or bad. The deep-dive nature of these old USENET posts archive the discussion excellently. Its a great snapshot into the thinking in 1993.
Your examples of CISC instructions are specialised, as one would expect, so maybe the earlier generations of engineers simply expected more specialised machines? Ironically perhaps, with the bitcoin era, there is now more interest in specialised machines again, though my impression is hardware manifacturers are more focused on practicality. Maybe people have realised the benefit of a general CISCy-RISC architechture for the sake of not wasting time with debate?
Overall, today's high-performance CPU programmers (and their tools: particularly their compilers) have a set of expectations, and CPU Engineers are designing their computers with those expectations in mind. That's really all there is too it.
Searching for snippets of this text in Google groups came up with some of the reposts, the earliest from 1993. But the original, which must predate that, didn't show up at all when I searched for it. That seems terrible. Moreover, the interface is poor. This invaluable historical material ought to be a far more available than it is.