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Comment by geogra4 | Hacker News Reader

yeah but how many nm are left? There's a phsyical limit to transistor size!

There is a lot of density that can be increased. The node size doesn't represent transistor size, not even the gate size.

What is the theoretical limit? I mean there should be end.

Well, the diameter of a silicon atom is 0.2nm, so I would guess it's at least that with silicon-based computers.

Not necessaraly.

The node size represents the equivalent 'gate' size of a standard transistor with similar performance characteristics.

By using better transistor designs, you can make the effective gate size much smaller than the actual gate size.

You can't make features smaller than one atom though, and silicon atoms in a crystal matrix are about 0.5nm apart.

The limit of information density is known as the Bekenstein bound.

https://en.m.wikipedia.org/wiki/Bekenstein_bound

It is derived through quantum mechanics and via the Plank constants and black hole physics.

Basically any more information squeezed together would turn into a black hole.

Though ordinary (non quantum) thermodynamics limits information density well before this bound.

As to what happens in the next decades with the good old Silicon stuff. Well, nobody knows just yet, but 3nm is what anyone realistically talks about, and just sci-fi tech after that.

Current density is ~100M (1E8) transistors/mm^2, Assuming transistors with a side of ~10 atoms (and bond length 0.5nm) that means we could get ~4E12 transistors/mm^2. This is almost certainly over optimistic but still it shows that we are orders of magnitude away from limits due to "atomic nature" of matter.

I think you first need to switch to transistors/nm^3 rather than thinking only in 2d.

Right now these are planar devices. If you stack you can get orders of magnitude more. That's why you can get absurd memory capacities in things like nitrogen defect diamonds [0].

[0] https://advances.sciencemag.org/content/2/10/e1600911.full

wouldn't that become a heat dissipation issue?

If you need to move charge then you get nasty joule heating, but if you only move spin density then this causes almost no heating (that's the promise of spintronics)

> There's a phsyical limit to transistor size!

The size of transistors themselves were not changing much during last few node transition, what shrunk was the space and wiring in between of them.

Remember the node size is more of a marketing term than anything now, and doesn't represent any actual dimension of the silicon.

7 -> 7+/P -> 5 -> 5+/P -> 3 are all in the works already and that's just TMSC

Those aren’t forgone conclusions. That’s just guesswork on a whiteboard roadmap. At 10nm we are already at a stage where quantum effects start to dominate, and it’s not clear how much further these classical effects can scale. 7nm was “a process too far” for Intel, and it is a bit of a miracle that TSMC managed to pull it off.

5nm isn't just on a whiteboard, it's in risk production already at TSMC. Volume production is slated for Q1 2020, less than a year away, and TSMC tend to be accurate with their estimates.

I hope you're right, but it's hard to imagine they aren't going to hit an unexpected wall at some point. The question is where is the wall? Basically you can never predict and unknown unknown.

>I hope you're right,

5nm started risk production were direct from TSMC report. They are expecting even faster ramp than 7nm. And TSMC has a history of being very conservative.

Their approach has been iteration rather than a leap like Intel did. And you can bet it will arrive on scheduled for next year's Apple iPhone.

There are roadmap, tools, technique for 3nm ( As explained in the Article ) and even 2nm. So none of these are pipe dreams. As long as these customers can keep paying top dollar to be on leading node, TSMC seems to have no problem with innovating. The question is when will these clients slow down and stop paying every year because leading node is too expensive. Basically the cost of designing leading node is doubling every two year. So we are seeing something like the inverse of Moore's Law.

I bet yes, just the top dog clients will have to change. See, semiconductor companies might look like quite formidable, but the Internet companies like Facebook, Amazon, Google actually have more money then even them. They will pay.

For consumer electronics, there is genuinely no benefits now going to smaller nodes, but for something like a "single chip supercomputer" type products, made with the most over the top semi tech, there is no better client than them.

For them, they are basically turning joules into ad clicks, and thus money, much akin to that bitcoin thing, which up until few years ago was one of the biggest semiconductor consumer globally.

> Internet companies like Facebook, Amazon, Google actually have more money then even them. They will pay.

I agree. And this is where the market dynamics changes, it will be interesting when the cost / economics model changes how things will unfold. Especially Amazon as they are already designing their own ARM CPU for Cloud Services.

Wouldn't smaller nodes benefit consumer electronics with lower power consumption at similar performance? Better battery life, etc.

Yes, but I think the cost of the chip (and cost per transistor on the chip) is starting to go back up again with each die shrink, rather than down every die shrink.

The performance of an individual transistor actually went down in 14>10>7 transition, but since you can pack more of them, the net effect is gain for companies with huge chips

I'm not saying they're pipe dreams. I'm saying things go wrong sometimes. How many companies have never missed a deadline? I'm not even saying that to be argumentative - I am genuinely curious.

It sounds like you're still not taking seriously the fact that 5nm isn't just planned, but already well into the execution phase. It's far enough along that the worst case scenario at this point would be for TSMC's 5nm to be much more usable than Intel's first attempt at 10nm. The horizon for really serious unforeseeable problems is well past 5nm already.

You could have said the same things about Intel and 7nm a few years ago. It’s not certain that they can de-risk it until they actually do.

>You could have said the same things about Intel and 7nm a few years ago.

Intel's 10nm and 7nm never went into Risk Production, Intel could lie about their progress because they were the only user of their Fab. And they never gave a precise definition, progress of their node, as they are not a Foundry business. Compared to TSMC Hundred of Customers relies on them being open and transparent with their progress. As long as Intel could continue to sell their Chips, it really doesn't matter which node they are on. Which is the reason Why Intel Custom Foundry never took off, they have held information to closely to themselves, and didn't treat their customer as parter in the likes of Samsung and TSMC.

I think an important difference is that EUV exists now.

That’s how you make the chip. I’m not doubting that you can get manufacturing smaller, for a while[0]. But will it still work? You’re getting into the domain where electrons start tunneling across transistors and such. There is a wall that we will hit where lithography can take us no further—we’ll need atomic precision to break through that wall. It’s just a question of where that wall is...

[0]: Higher frequency UV light is more tightly focused, but also imparts more energy. At some point the blasting power of a single photon does damage on a scale larger than the wavelengths involved, at which point EUV will take you no further.

> There is a wall that we will hit where lithography can take us no further

This is something being said every few years. There were times when people were telling of 1 micron being "the wall."

Transistors at 7 & 5 are nowhere close to having serious “quantum” issues—that regime is thousands of times smaller than current gate design. Remember that the “size” is a marketing term that really relates most closely to “effective” wire pitch & gate density with respect to processes in the hundreds-of-nanometer scale. The absolute smallest functioning design I’ve read about is IBM’s 7-atom gate. That gate is something like 100thousand times smaller (volumetrically) than current production.

Also, current HW design is really inefficient. Think about all the crud between some front-end developer and the server powering the webpage on the backend, vs a ‘native’ app. That’s a good analogy to current HW design and real total-badass low level HW design.

Arguably, everything about a mosfet is a quantum effect.

But anyway, undesirable quantum effects have been problematic for almost a decade, and were overcome with a variety of techniques (inc FinFET).

I've heard about TSMC working on so-called "3nm", so while I don't know whether it approaches physical limits (those nanometers are just marketing speak after all), it's certain that we have another 10-15 years of progress ahead of us.

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