Is this really the case? The timing parent is talking about is fractions of a cycle, maybe five orders of magnitude above audible frequencies.
How could you take advantage of exposed timing?
How could you take advantage of exposed timing?
2) low latency processing of the above may require in-situ pipelining in which the pass-through buffer itself IS the processing buffer, etc. imagine being able to eat the pot you boil your pasta in.
3) why WOULDN'T any well-designed elegant system have every single tick as a function of that bit clock? It makes no sense to deliberately place spanners in your own path, particularly as pertains to jitter etc. It's not like you are going to pause your wavelet transform and check your email in process...
Removing precise control over timing from the language stack one uses to program FPGA's with is removing a desirable feature for many of their uses cases.
If one is interesting in glossing over all this abstraction, why is one wishing to use an FPGA at all?
I will reverse the question and say: "in which scenarios is someone hoping to avoid addressing precise timing constructs in FPGA programming?"
Obviously I'm not referring to clock propagation delay or quantum entanglement etc LOL I mean the intentional macro stuff wrt "timing"
If you're talking about higher level timing, nobody is arguing for taking that away from you.