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Comment by phkahler | Hacker News Reader

Has the vector spec been finalized yet? I think it will be critical to bring graphics to RISCV.

It's still a work-in-progress, but there should be some interesting news at the RISC-V Zurich conference next week [1]. For example, Imperas has announced an ISA simulator for the current 0.71 version of the specification [2].

[1] (https://tmt.knect365.com/risc-v-workshop-zurich/agenda/1)

[2] (http://imperas.com/articles/imperas-delivers-first-risc-v-si...)

> at the RISC-V Zurich conference next week

Curiously this session is only 15 minutes long. June 11, 17:45 - 18:00, by Krste Asanovic.

Nevertheless it is quite promising:

"Vector Extension 0.7. The vector extensions have reached a major milestone with the release of version 0.7, which is intended for widespread implementation and comment".

Excellent news.

There were a ton of talk submissions, and the schedule is incredibly tight because of it. =(

Graphics is much more subtle than just vector instructions as can be seen from the failures of Larrabee.

I'd imagine Larrabees failures primarily has been being competitive with AMD and nVidia?

Larrabee had dedicated texturing hardware, but management decided to not expose it or try shipping it as a GPU.

>> Graphics is much more subtle than just vector instructions as can be seen from the failures of Larrabee.

It is. But given there are zero other open source solutions, I think LLVM Pipe running on the vector extension would be a decent option. It's not going to compete with the big guys, but it will make SoCs possible without licensing grahpics IP.

Yes. But the RISC-V Vector instruction will serve as the baseline. And further extensions will add register types, Esperanto is already extending them with graphic types.

Note that RISCV vector extension also supports matrices, tensors, etc. So at least for GPGPU compute applications, it feels quite modern (e.g. Volta has tensor cores).

Also, Larrabee had fixed-width 512-bit wide vectors (it did not support SSE 128-bit wide or AVX 256-bit wide vectors). RISC-V has Cray vectors of dynamic length (e.g. need a 128-bit vector, no problem, need a 4096 bit one? no problem either).

I think the main issue for programming CPUs to solve GPU problems is that our programming models for CPUs don't expose the memory hierarchy, while the ones for GPUs do that in a much more finer grained way.

Memory bandwidth is another issue holding CPUs back

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