The power dissipation problem of current chips (performance is almost always power/thermal limited) is correlated with 2D structures. Communication is one giant problem: 3D structures could allow for far better colocation of connected compute elements, so we might not have to spend most of our power budget feeding data in and out of compute clusters. Scaling in 2D does make this problem easier (in some ways!), much as adding a 3rd dimension would too.