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Adapt a perfectly working machine to a mental crutch instead of learning data oriented design?

If this means running millions of already written programs more efficiently - yes!

The question is whether those gates are really best used for this feature. Also, this feature might increase latency and make tens of millions programs run slower.

It probably can be done generic enough in a cpu, reordering data layouts on the fly using some access and temporal locality tracing like done for caches. Slight memory cost.

Security implications are important though, with programmer nor kernel no longer controlling memory layout.

Initial stages of this are already seen in the various ways of memory interleaving for multiple banks, cores and cpus.

The truly fun part would be speculative as opposed to tracing reordering...

Compression could potentially help bandwidth, but it isn't going to do anything for memory latency, which is the actual problem. That being said, if compression is part of a CPU cache it could indirectly help, but then I'm not sure how that is going to be done on 'objects' (whatever their definition is).

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