Intel XED – x86 Encoder Decoder

Intel is releasing the source of XED but canceling IACA which is built on top of XED. Color me confused. Still, this will be useful for a lot of projects to have this piece of infrastructure for such an important CISC ISA available under an Apache license. Boring as hell, but useful.

For example, ARM tests their ARM LLVM backend using a golden reference implementation. This is the MC Hammer test: encode/decode assemble/disassemble[1]. This can be the golden reference for the same with x86_64 and useful for GCC+LLVM.

[1] https://llvm.org/devmtg/2012-04-12/Slides/Richard_Barton.pdf

There was a talk at Recon several years ago by Richard Johnson called "Go Speed Tracer" that goes into some of things built with a tool like this. Its a serious talk, dense with information, covers some guided fuzzing territory and alot about tracing engines (hence the name). He mentions xed by name in the talk and notes interestingly enough that despite Pin and xed being developed inhouse at intel there isn't a one-to-one parity between the silicon and the disassembler and subsequently Pin itself. Glad to be able to sift through the source now, thanks for posting this 'peter_d_sherman

Link for the talk https://www.youtube.com/watch?v=oWKDaD9wrWo

Anyone interested in accurate (and fast) instruction decoding for x86(-64) should also look into Zydis: https://github.com/zyantific/zydis

Anyone done any work to confirm how accurate XED is? Do all the decoded instruction lengths match with real hardware? Sure, it's from Intel, but I'd like to have something more. Other x86 decoders could have been better.

MAQAO (http://maqao.org/) might also be of interest.