I use it in my presentations' HTML files to add computed content, such as the results of running code, or more complicated tables and diagrams.
We have something at work that's very similar but perl-based for our VHDL source. It saves a lot of boilerplate for conversion functions, null types, read/write cpu functions etc. Vhdl has pretty awful templating so it's really useful, you just need to use it sparingly else it becomes unreadable very quickly.
I do this using cog for Verilog code. It lets me generate signal processing constants/math in the signal processing code itself, driven by a single control file (with, i.e. system sample rate) without having to rely on Verilog's awkward (where even available) math.
Could be useful for templating config files. It sounds a lot like Jinja2. The question for me is what makes this better than Jinja2?