Very interesting technique. I remember when they would reverse engineer chips by grinding them down while taking nice pictures of each layer for the engineers to interpret later.
At a prior job last decade involving FCBGA packaging design for the company's ASIC, and I witnessed exactly this to debug ESD problems, etc. That is, prototype dice failing test would be ground down until a black spot was found. Very expensive design cycles, so lots of incentive to extensively model such issues before fab.