Darpa teams up with NSF to develop ASICs tailored for ML applications

mil-embedded.com

62 pointshhs3 comments

Using Tensorflow to generate Verilog to run Tensorflow? That’s s flywheel that could destroy the universe.

In all seriousness, this is cool. Are there any writeups about the state of ASICs for ML? I understand Google TPUs to be the same thing but I have no clue what’s going on under the hood.

Google Brain team homepage is a good general source of information [0], and the HotChips [1] conference is perhaps the best source for research information regarding latest ML ASIC designs from Google [2], Intel, ARM, Wave, IMG and others. Google TPU3 systems are discussed extensively, here [3].

[0]: https://ai.google/research/teams/brain [1]: https://www.hotchips.org [2]: https://www.hotchips.org/wp-content/uploads/hc_archives/hc29... [3]: https://www.nextplatform.com/2018/05/10/tearing-apart-google...

Thanks for sharing, it looks like a livestream of the event will be hosted, here: https://www.youtube.com/watch?v=wuvCx6sFvt8

I've tried to ask whether registration is required (ie., for non-US citizens) but there was an error with .mil email address. Posting here in case someone from DARPA is reading: `local-part of envelope RCPT address contains utf8 but remote server did not offer SMTPUTF8.`

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