Memory Models: A Case for Rethinking Parallel Languages and Hardware (2010) | Hacker News Reader

Memory Models: A Case for Rethinking Parallel Languages and Hardware (2010)

cacm.acm.org

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Since this is about parallel languages, why don't they say anything about Erlang and related languages?

Erlang has a trivial memory model, so it isn’t interesting in an article about the challenges of memory models.

The article says a lot about concurrent programming, but little about parallel programming.

The naming is misleading.

It's tricky: https://www.quora.com/What-is-the-difference-between-concurr...

But a language that is concurrent and not parallel will usually (always? can't think of a counter-example) have a full memory barrier on a context switch, so the memory model is simple. I think that's why it's relevant to many parallel programming models, but not concurrent programming ones, and why the title is as it is.

The naming is not misleading, because the article says a lot about parallel processing.

It is talking about memory consistency models, for heaven's sake. If you have a uniprocessor, or any kind of concurrency without parallelism, it makes zero sense to talk about memory consistency models because you automatically have sequential consistency and don't have to think about it.

If you don't have a multiprocessor, you don't need to think about memory consistency models. If you have a multiprocessor without parallelism, that's your problem, not the author's.

Unfortunately because of compiler optimizations, memory models are important even on uniprocessors.

Sure, and the article discusses that. I was thinking at the instruction level. I tend to think of convincing the hardware to do what you want and convincing the compiler to do what you want separately as an effect of writing code before the languages had specified memory models.

EDIT: Though as I think about it I'm having a hard time thinking of a system in which those compiler optimizations are problematic on a uniprocessor system. It is definitely true that optimizations that are safe on a uniprocessor break on a multiprocessor, but I can't think of any systems that don't (effectively) have a memory barrier when switching between threads. SMT wouldn't see a problem because both threads are on the same processor.

Imagine implementing a simple spinlock, but then substituting relaxed atomics for acquire/release synchronization. The compiler can reorder taking the lock relative to the protected operations and render the lock useless.

Thanks!

I think there are two ways forward; larger L1 caches or split memory between cores, both have their problems.

To solve what this article argues about though, you can use my internet platform: https://github.com/tinspin/rupy

Java has excellent concurrency and non-blocking implementations.

Since it also has the only class-loader that is worth using, it's the only programming language you can use for server-side joint parallel future proof systems today.

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