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Comment by twtw | Hacker News Reader

I need to take a look at the patches (on mobile now), but can anyone comment on how a barrier at unlock can provide ordering between mmio accesses under the same lock? Or is it required that every register have a unique lock?

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It doesn't, this is about this case:

  CPU1:
  lock()
  write1
  unlock()
  
  CPU2, after CPU1:
  lock()
  write2
  unlock()

Until now it was not guaranteed on all platforms that the writes arrive in the same order even if the CPU2 entered the critical section after CPU1.

This was because spinlocks only implied regular memory barriers, not mmiowb barriers.

I don't think this is meant to remove the need for explicit barriers if a single function is performing a multi-step process of interacting with a MMIO device, such as a complicated initialization that requires writing some registers, reading the result from some others, and then writing to some more. Instead, this seems to be about synchronizing cases where multiple functions running on different threads may want to simultaneously interact with the same device.

I don't really have any idea of the relative frequency of those two cases.

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