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Comment by henrikeh | Hacker News Reader

It might seem wasted, but the reality is that a “standard” footprint does not really make sense. Soldering and assembly is not a perfect craft and it requires hundreds of considerations to methods used, environment of use, desired reliability etc. for example look up the footprint differences for wave soldering compared to hand soldering. For aerospace use reliability is king, for mobile devices space is a premium.

Furthermore, there aren’t really any standards for packages and hence it is difficult to trust foorprints. A TSOP package from one manufacturer manufacturer is not necessarily the same as a TSOP package from another. This is not a hypothetical — I’ve been bitten by this.

There are tools to assist in and automate a lot of this, but since most of the time is spend on other parts of a product it simply isn’t very critical.

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A standard footprint might not make sense, but a standard format for distributing component pad placement definitely does. Most ECAD systems already have tools in place to generate proper landing pad offsets from footprint.

And you're right that one can never fully trust downloaded libraries, but a lot of the issues could be mitigated if manufacturers distributed their own files. TI does this for most of their devices and it's a big draw for a lazy designer like me.

I'm really surprised there isn't a better solution in the industry - building a library might not take as much time as the rest of electrical design work but it's still a large sink, to where many teams (even as small as 6 engineers or so) result to hiring a full time "librarian" to manage footprints and component libraries.

While manufacturer's may have very small deviations in their footprints, by and large almost every IC conforms to some kind of JEDEC compliant package. From there, IPC-7351B [1] has mathematical recommendations on footprints ranging from Class 1 (minimum required) to Class 3 A/B (ultra-reliable). Obviously those are just suggestions, but manufacturers have been aligning more and more with them. My daily ECAD/EDA tool is Altium, and I can't remember I had to manually make an IC footprint. I use their IPC Wizard[2] to make it all for me. As a bonus, I get a nice STEP model too with my export.

[1]: Can find it here http://shop.ipc.org/IPC-7351B-English-D or likely in PDF elsewhere. [2]: https://www.altium.com/solution/pcb-footprint-library

An appendix.

A lot of good stuff has begun to happen in this regard. At least KiCad has a large and pretty decent quality collection of footprints; I think other tools are making similar efforts.

However, I wish they would make it easy to adjust these footprints or make derivatives of them, without having to essentially redraw them.

For a looong time I’ve wanted to apply geometric constraint solving to drawing footprints. This would allow for having a base footprint which defines the constraints and then parameter files could introduce the specific dimensions needed. I’ve been working on it at https://github.com/henrikh/footwork-ecad and the parts are there, but I’d love to collaborate on it with someone :-)

Hey, I'd be up for collaboration, what are your plans for this?

For a long while geda's pcb used mostly parametrized footprints written in M4. People mostly hated them.

If one is wandering into that path, the hardest problem to solve is defining a good language/library in what people can describe them.

I think OP was maybe hinting that footprints could be distributed in a machine-readable format, rather than pdfs with diagrams on them.

>> For aerospace use reliability is king, for mobile devices space is a premium.

That's a great point. But how many different footprints need to exist for a 1206 led package from one manufacturer? Infinity? Or is it something more like 5?

>> A TSOP package from one manufacturer manufacturer is not necessarily the same as a TSOP package from another. This is not a hypothetical — I’ve been bitten by this.

But that's a different issue of a manufacturer not conforming to the spec they've published for their product. Same as a carabiner failing at a load of 100kg when it's rated for 500kg.

>> But that's a different issue of a manufacturer not conforming to the spec they've published for their product. Same as a carabiner failing at a load of 100kg when it's rated for 500kg.

Package names are, in some fashion, marketing and branding. The manufacturers publish their own specs and do adhere to them. There are also standards (mentioned in other comments), but they are typically more general.

I’m not saying this is ideal – but that is simply the reality.

> A TSOP package from one manufacturer manufacturer is not necessarily the same as a TSOP package from another.

Yeah, I've noticed this too. I now have to check the specific measurements (pin pitch etc) in the datasheets before buying, regardless of what the product page states about packages. I still on occasion make mistakes and get super tiny packages that I can't use without a pick and place machine...

This is mostly caused by both manufacturers and footprint library authors/EDA vendors using their own nomenclature for packages instead of the JEDEC standard names. This is especially apparent with gullwing SMD packages (anything from SO(IC) to LQFP) which are mostly same across manufacturers but vary widely in what they are called.

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