Would have been awesome if they joined the effort of developing FIRRTL[1][2] and using it as a universal (LLVM-alike) hardware intermediate language, better suited modern chip design needs than Verilog or VHDL[3].
[1] https://github.com/freechipsproject/FIRRTL
[2] https://aspire.eecs.berkeley.edu/wp/wp-content/uploads/2017/...