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So this is the logic of the controller in Verilog. But I don't see any test scripts. I am not an expert in logic design, but it seems to me that validation is at least as expensive and time consuming as the actual creation because you cannot afford mistakes in the ASIC masks. Am I missing something here?

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You are correct. The most difficult part of a design is not the design itself, it's all the documentation and the verification environment around it.

This is a nice gesture but hardware is a bit different than software and dumping a bunch of RTL code is not really useful.

A full environment that could get you to a blinking LED off of an FPGA would be the complete dump, but I don't see the value in downplaying publishing a bulk of code that all others have hidden behind lock and key.

https://github.com/westerndigitalcorporation/swerv-ISS

From a quick look this is a reference model, not a testbench. There is a lot of work needed, writing testbench environment, test cases, analyzing and writing coverage models etc. before the Verilog code can be considered verified and ready for ASIC tape-out.

From my experience writing the design RTL code is at most 25% of the man hours. The rest is verification and some synthesis backend work.

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