Intel Unveils a Groundbreaking Way to Make 3D Chips | Hacker News Reader

Intel Unveils a Groundbreaking Way to Make 3D Chips

engadget.com

Engaget has an annoying cookiewall, could we have literally any other article based on the same press release please? (Or ideally the underlying PR)

https://hothardware.com/news/intel-foveros-to-usher-in-indus...

https://arstechnica.com/gadgets/2018/12/intel-introduces-fov...

(maybe underlying PR?) https://newsroom.intel.com/articles/new-intel-architectures-...

Responding to the actual technology, the key is what they call "Foveros" or "active interposer". Previously chips were limited to having interconnect on one side: the traditional solder bumps. It appears that not only do they have through-silicon vias working but they have combined this with having logic on the die - typically this is a problem because the more complex the logic is, the less flat the active side is. The actual layer thickness will vary across layers and across the die by tiny amounts.

This is basically the silicon version of mezzanine PCBs: you can stack a fully-capable logic chip directly on top of another chip, usually for handling the IO. The example then also has some DRAM stuck on top with standard package stacking technology like the Raspberry Pi.

i think their cookiewall may depend on js. i'm blocking both of them and can see it fine.

Anandtech's article is even more detailed and has a reasonable interesting interview at the end.

https://www.anandtech.com/show/13699/intel-architecture-day-...

I work for Intel on a team that partners w/ design and manufacturing to build DFX features and tooling. It's been quite the ride to enable DFX for Foveros but it's really exciting technology.

At the end of the day I look at it like this: it's getting harder and more expensive to reduce nano-meter size, getting high yields on 5nm, 3nm and beyond is going to be a multi-billion dollar effort for everyone in the industry, with Foveros we can really squeeze water from a rock and build products on advance node tech even if overall yield isn't the greatest.

I don't think it's a shock to say that the 18 month window described by Moore's Law is probably well behind us. But new innovations like Foveros give me confidence that we still have a long road ahead of us to improve silicon performance.

Glad to see more semiconductor folks here! Thanks for all the hard work making the design rules work for this process.

Do you know if there are any real papers detailing Foveros?

There may be some white papers floating around describing the tech but to my knowledge no academic level papers have been released yet.

Do you know what is Intel's yield on their 10nm process?

I do but am not at liberty to discuss.

In undergrad and a little bit into grad school, I did some 3DIC research. It was interesting stuff and really exciting to expand architectural design into 3 dimensions.

The biggest problem was heat as the additional layers trap heat in the chip and make it much easier to let the magic smoke out.

I don't see much in this article explaining any groundbreaking approaches and the diagrams offered look much the same as they did 5 years ago.

"additional layers trap heat in the chip" is this really such a huge problem? Many people immediately conclude that this can just be solved via a convecting fluid.

Hope your fluid can circulate in micrometers between sandwiches of silicone. I bet it cannot.

Even pure metal solder has limited thermal capacity. Enough that people got mileage from milling down micrometers of chips...

The other side becomes less conductive too.

Verging on the dramatically mechanical what about using a low friction ultrathin tape?

> Many people immediately conclude that this can just be solved via a convecting fluid.

Many people have physical intuition that treats fluids as inviscid, or at least neglects the effects of scale and viscosity.

Alternatively 3DIC invites power efficient architectures which scale transistors over power per transistor. Such that you might have many more processor cores / stream processors, clocked much slower, at lower voltages.

The real problem as I see it, is that producing 3D chips is uneconomical for most cases. You either need to stack dies (expensive), or produce layers of transistors, incurring more lithography / etch / mask steps (slow and expensive). So it mainly makes economical sense in area constrained scenarios.

I don't believe anything Intel says in a press report until I see the actual product. We have been lied to and mislead too many times.

I could not care less about an actual product. I just want them to convince AMD and Arm that they might be delivering a Moore's law equivalent performance improvement.

Sounds like one of several backup plans to make decently powerful CPUs next year despite dropping the ball on the 10nm process; it's probably mature technology, slightly anticipated from its planned debut (did you notice the slides mentioning the 10nm process?).

In sadly related news, the presentation of "Sunny Cove" CPUs (which might or might not use these packaging techniques) mentions the 14nm process but not the 10nm or 7nm ones, brazenly proclaims an "age of architecture", lists boring incremental improvements and doesn't even try to discuss performance, core count or power efficiency.

Chips already get to 100 degrees Celsius with just one layer of transistors: how does thermal dissipation work when you're stacking 'chiplets' on top of each other?

I'd imagine integrated channels for liquid or evaporative cooling would work quite well. Something like a 100 micron diameter tube every square mm or so is in principle totally doable.

Obviously a non-trivial engineering challenge but nothing breaking the laws of physics.

No they don't. You cannot circulate fluid at micrometer spaces at speed - huge forces are required. (Try it at home, push two panes of glass together and try to push water through. Good luck. You'd crack the glass first and silicone is even less resilient...)

Capillary action works but it is too slow to make a dent in cooling. Heatpipes need like a few milimeters of such micrometer fabric to work reasonably well. Even solid metal mesh is not good enough at the available thickness. (And its capacitance will pose a problem.)

You'd have more luck integrating power hungry thermoelectric components to push heat at huge power cost... (since you will be using exotic materials soon anyway)

You vastly overestimate the forces required. Pumping water, let alone a less viscous organic fluid at a few mLs per minute through nominally 100micron pipe is fairly routine. You wouldn't even need 100psi to move a few mL/tube: plenty to absorb the heat output from a fraction of a processor layer.

Few mL/min is not enough cooling, that's the point. Way not enough to make a dent. Vapour phase is used in GPU interface already and is comparable to solid copper but lighter, why do you think merging a heatsink with the CPU will work when Intel has trouble even soldering the devices and leaves thick silicone layer on top?

We're talking about something to remove many watts. This means huge capillary volume to compensate for low flow. Which means a lot of heatpipe surface soldered somehow to IHS.

You'd have more success with solid copper layer which is sort of done where possible. (It's often not due to inductance.)

math:

200W output per CPU 'layer' on a 17x17mm* die = 17 x 127micron tubes flowing 25mL/min each at 160psi (easily reducible with moderately larger capillaries) totals 425mL/min. 425mL/min of water starting at 30C and ending at 75C would absorb 45C * 425mL/min 4.16J/C = 79,560 J/minutes or 1,300 watts - about 600% of requisite cooling capacity.

nominal threadripper #'s

http://www.waters.com/webassets/other/lp/prep_calc/Tubingand...

> It's developed the first 3D chip architecture that allows logic chips -- things like the CPU and graphics -- to be stacked together.

So, they just have a theoretical architecture, is that it ?

What about that sentence makes it seem theoretical?

I would read the article, but the site refuses to load any text if javascript is disabled, so tough luck for engadget.

Here is their PR page for it https://newsroom.intel.com/articles/new-intel-architectures-...

"Intel expects to launch a range of products using Foveros beginning in the second half of 2019."

That timeline implies they've done the internal technology demonstration and the implementation is somewhere in the tapeout process.

What is the difference between this and multi-die stacking? NAND memory packages typically have up to 4 (8?) dies stacked together. Is this something beyond that?

Hah, that's a good name. It means "terrifying" in Greek.

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