Are you referring to iq modulation here? So in practice they have two 61 MSPS ADCs? I guess it makes sense then to have twice the bandwidth too.
I haven't studied the BladeRF layout, I can just tell about the Ettus USRP. There, the receive path looks like that:
[Antenna]---[ADL5380 Quadrature Demod]===[2x low-pass filters in parallel]===[2x ADC in parallel]
Then you have digital data that is fed to the FPGA.
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