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If you're missing the factor two, as in "sampling frequency must be twice the maximum signal frequency", the keyword is complex sampling. With complex signals, the sampling theorem is "sampling frequency must be greater than the maximum signal frequency".
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I don't want to make anybody read about sampling. So we have a real signal - we're in the real world - and suddenly there's a complex signal? You basically fork the signal, and delay one signal path by half the clock period. You can then sample both signals at the same time, and collect the data you would get when sampling with the double frequency. Because we sample two signals, we store two samples at a time. One we call the real signal, one the imaginary -- and there we got our complex signal.
I haven't studied the BladeRF layout, I can just tell about the Ettus USRP. There, the receive path looks like that:
[Antenna]---[ADL5380 Quadrature Demod]===[2x low-pass filters in parallel]===[2x ADC in parallel]
Then you have digital data that is fed to the FPGA.
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