It's worth point out that there are still plenty of static RAM in modern chips and those obviously don't require refreshing. The CPU cache would be an example, but there are also plenty of internal SRAMs in ASICs and FPGAs everywhere.

The refresh needed by DRAM is also why you can't merely suspend-to-RAM by merely keeping it powered up, the bits will flip. You need a special self-refresh mode that keeps updating every cell.

While implementing suspend-to-RAM on an embedded system I wanted to test that my self-refresh was working correctly, so I decided to test the null hypothesis: I'd suspend my ROM code without enabling auto-refresh, wait a second or so, wake up and smell the ashes. Except... it seemed to work anyway. The data was still here.

It turns out that while the refresh period of DRAM is usually a handful of ms at most, you will still have a relatively low bitflit rate even after several seconds. In hindsight it makes sense: in production you want an error rate of effectively 0% (especially if you don't have ECC) across potentially billions of cells. Most cells can probably hold their value for much, much longer than the refresh period but you need to catch the full bell curve and it needs to keep working across the entire temperature and voltage range for all chips.