Cascade: A Just-In-Time Compiler for Verilog

Compiling for simulation usually pretty quick. Depending on how many clock cycles of stimulus coded into your simulation, the execution of the simulation can be also be pretty quick or hours and hours long.

Compiling for the FPGA usually takes much longer than compilation for simulation. Running the same number of clock cycles as your simulation is much much faster in using real hardware (FPGA) than the simulation.

Reading the description in TFA, it sounds like this tool does both types of compiles. I hope I have more time to play with it soon, because it sounds like it even offers to produce a complete software/hardware system out of your verilog (not all legal verilog syntax can be compiled to hardware, but it can all be compiled to a software executable).

I'm not really sure such a thing exists (or can exist). Verilog isn't "programming" in any way most developers are familiar with, it's a way of describing how logic gates are interconnected. An understanding of digital logic is necessary to use Verilog/VHDL successfully.

That being said, you might take a look at Brown's "Fundamentals of Digital Logic with Verilog Design", which seems to cover the topics you'd need to succeed.