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Comment by kev009 | Hacker News Reader

The cpu also has typically multiple independent CPUs to control things like power saving and turbo boost. Modern intel cpus have multiple 486-class CPUs, one for this, one for the ME, and one that vendors can use that has SMM access (which is as scary or more so than the ME).

OpenPOWER is pretty neat because you can actually see what commercially relevant implementations of these firmwares look like https://github.com/open-power/occ

A lot of NICs are also completely based on multiple general purpose MIPS cores like Broadcom and Mellanox. The most common SAS HBA from LSI/Broadcom was a PowerPC SoC. And SATA/SAS drives are running multiple ARM Cortex M series MCUs for the bus interface, drive geometry, and FTL in the case of flash.

The BMC (IPMI) is also a self sufficient ARM computer.

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> And SATA/SAS drives are running multiple ARM Cortex M series MCUs

http://spritesmods.com/?art=hddhack

To be totally pedantic WD HDD controllers are Cortex R cores, shifting to RISC-V.

Compare it to the straightforward days of yore, when my hard drive controller only had a Z80 and my printer an MC68000.

Or my floppy drive had the same CPU and roughly the same clock as the computer...

C64? Or was there some other system that was true for?

I thought SMM was just a special mode of the main cpu itself?

Yeah, SMM is just Ring -2 on the main cores.

> The BMC (IPMI) is also a self sufficient ARM computer

ASPEED BMC SoCs (popular BMC SoCs also used in OpenPOWER systems) have a ColdFire (m68k) co-processor buried inside them. In OpenPOWER OpenBMC firmwares we use the ColdFire to bitbang a JTAG-ish protocol into the POWER chip

Writable microcode?

If it's anything like Cell, it's just a bunch of fairly boring configuration information. If you want to dig in more it's called the "Configuration Ring". It's an about 2kbit SPI ring that has stuff like memory timings, and all the stuff that might get fused off for binning. On the PS3 you could try and turn on the SPE that was disabled by playing with the config ring, and see if you got lucky and had a perfect chip.

Does MIPS have some advantage for applications like NICs, or is it just a matter of using what they’ve been using?

It's just hard to beat MIPS perceptibly at perf/gate at the gate counts they're willing to expend, but that's more or less true of any not braindead RISC. Beyond that it's just one of those "it's what we've always done".

Sort of like how HBAs had i960s for an obnoxiously long time. For what ever reason some Patterson & Hennessy 5-stage RISC gains a foothold in an embedded niche and it's hard to make an argument to switch. RISC-V has the best argument right now; it's hard to beat zero licensing fees.

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