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Yes, I want to work on that. I agree with you 100% that this is what the world needs. GNU succeeded by replacing commercial tools, not inventing new languages or paradigms. There is a ton of existing, legacy Verilog and VHDL code out there being used in current designs and nobody is going to switch to Free tools unless those tools support that legacy code.

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Ok, let's get started. We need an abstract simulator front end, and to be able to connect that simulator front end to both Verilog and VHDL - almost like a simulator IR language, and have that language cover productions from both VHDL and Verilog. There's some recent Verilator optimazations to look at, but all that stuff comes later. V0.0 should probably just have a simple message pump for delta cycle emissions. I'll start seeing if I can gather some literature on this.

Cool. How do we get in touch? I don't really want to put my email address in a comment here...

Are you going to track the progress somewhere? I'm interested in helping

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