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Comment by gravypod | Hacker News Reader

How would one build an asynchronous implementation of this circuit in an HDL

It's easy to do this. See this part? It's repeated 32 times.

       // Compute mode.
        cos_next = cos + (direction_negative ? sin_shr : -sin_shr);
        sin_next = sin + (direction_negative ? -cos_shr : cos_shr);
        angle_next = angle + (direction_negative ? beta : -beta);

What you need to do is make 32 instances of this in series. Then you can compute the sin and cos without any flip-flops, which counts as asynchronous. beta is an array indexed by count, so this will instead be replaced with `BETA_0, `BETA_1, etc. for each instance.

A pipelined version is more useful: you still make 32 instances, but leave flip-flops between each stage. This way you produce one result per cycle, but with a 32-cycle latency. The cycle time is fast since there is not much logic in each stage. This might be useful, for example, to make the logic part of a DDS.

Why?

Replying because I can't edit.

This is way too complex, a purely combinatorial version would never meet timing in a design where you cared enough to make it in an FPGA. The question doesn't make sense on it's face. You want a pipelined version.

I asked why to get to the bottom of wht he's really asking.

You could use multi cycle paths so this doesn't limit your global timing. Then you would save the registers. This is much more useful for ASIC design, because on an FPGA the registers are there whether you use them or not.

However total latency will be lower than a pipe-lined version which is nice if that's what your optimizing for.

Yeah, but if you were using a more advanced technique like that, you wouldn't be asking on HN how to unroll that loop.

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