The mysterious processor behind China’s first homegrown supercomputer | Hacker News Reader

The mysterious processor behind China’s first homegrown supercomputer

smartplanet.com

25 pointsukdm25 comments

MIPS processors in general, haven’t been tested in the context of the modern supercomputer

O RLY? Someone ought to tell (what's left of) SGI about that.

Sgi started switching to x86 for their supercomputers quite a while ago

Yes that it true, however it is also true that they were making 2048-CPU MIPS IRIX supercomputers before that, so to claim that MIPS is untried in the massively-parallel space is untrue.

Of course, that whole 2048-CPU IRIX machine was probably about as fast as a modern high-end video card.

True, though until semi-recently SiCortex offered MIPS-based HPC/supercomputer systems -- sicortex.com has been offline for a while, but see: http://en.wikipedia.org/wiki/SiCortex

MIPS was a bloody good processor, had SGI held their nerve they might be now where Itanic is today... Umm.

8 core per die MIPS based processor at 1Ghz.

Not much else to the article other than a "China doesn't need Intel/AMD theme".

This seems like a bad idea.

Let’s assume it costs a few million to design this chip, well you can already buy a an i7 which has 4 cores runs at 3.06GHz costs about 250$ in bulk. That’s 4,000 CPU’s per million in development costs before they see a single CPU off the line. If they get something 20% better then they are looking at a few hundred thousand chips to break even.

PS: They suggest that it’s going to be 30% slower than a 6 core chip which suggests it’s on par with a current generation chip 4core CPU.

China wants to be independent as far as computing goes. That is all.

There are plenty of reasons to build your own chip's. For example, NSA was doing so, and probably still does. But, it only worth it if your making something dramatically different than an x86 CPU.

The problem is keeping up with Intel is a ridiculously expensive proposition. analysis showed Intel's R&D expenditures were $22.1 billion between 2001 and 2005 http://www.emsnow.com/newsarchives/archivedetails.cfm?ID=136... Either staying a few generations behind and building more chips, or buying from the beast seems like the best option.

PS: Intel does manufacturing in china (http://arstechnica.com/hardware/news/2009/06/intel-china-fab...) so they already have access to slightly behind the time manufacturing technology.

Hmmm. Could this possibly be something to do with US supercomputer export controls? Don't know much about this but a quick google showed that the US has been tightening controls lately.

I wonder what people are using supercomputers for in the military these days anyway - UAV? Crypto? I'm guessing ballistics is pretty well solved. And you hear the occasional story about suits showing up and requesting that labs disable-in-hardware the execution of Shor's algorithm on their quantum-related tech...

Nuclear weapon R&D. That's how the 5 weapons states acknowledged by the NPT have been able to maintain the unofficial test moratorium - all the supercritical explosions are happening in simulation.

cost does not matter when it means you can have an independent processor family to control your nuclear missiles.

Given China's proclivity for stealing tech and previous history of stolen processors I'll believe this is evidence of China's R&D capability when an independent 3rd party tears the chip down.

The Loongson family was developed at the Institute of Computing Technology in China. It's based on the MIPS design but the original processors were missing 4 instructions covered by MIPS Technologies patents.

ICT now licence the MIPS architectures directly from MIPS Technologies, so there's nothing stolen about it.

I'm not sure if you didn't read the article or are unfamiliar with the MIPS platform, but it is widely licensed and still widely used in certain embedded segments.

http://en.wikipedia.org/wiki/MIPS_architecture#Licensable_ar...

My first thought upon seeing the headline was "IP theft" too.

I'm familiar with MIPS, I'm was referring more to the specific implementation and fabrication technology.

Since when is MIPS mysterious?

Hell, I even know a small bit of 64bit MIPS assembly...

Yeah, I know a bit of MIPS assembly as well. It was my understanding that MIPS was the standard assembly to teach. Though, this is just through the narrow lens of my life. At my school, when you learned assembly, the first one was generally MIPS.

We learned x86 first and then MIPS. We went in pretty deep with MIPS though, going so far as running our programs in a simulator which visually showed the states of the different pipeline stages as the instructions were executed. It was a pretty interesting course, actually. At the end, the lecturer gave us a competition where the person who could sort a list of numbers in the fewest cycles won. I implemented quicksort and I think it took something like 10K cycles to sort 100 numbers. I think the median in the class was 20K and the best was 6K. Fun :)

It's not mentioned in the article, but Loongson 3 adds instructions specifically to support Intel emulation. According to Wikipedia (http://en.wikipedia.org/wiki/Loongson):

Loongson 3 adds over 200 new instructions to speed up x86 instruction execution at a cost of 5% of the total die area. The new instructions help QEMU translate x86 instructions by lowering the overhead of executing x86/CISC-style instructions in the MIPS pipeline. With additional improvements in QEMU from ICT, Loongson-3 achieves an average of 70% the performance of executing native binaries when running x86 binaries from nine benchmarks.

Trivia: rms uses a Loongson powered laptop.

MIPS processors are a tad bit more exotic than CISC or RISC architecture, but hardly mysterious. Hell, the PS2's main CPU was a MIPS processor and plenty of people have tinkered with it for various things, including a super computer: http://www.geek.com/articles/games/researchers-create-a-play...

Why post a link to this nothing article on HN? There is nothing new here except for the misconceptions of the authors.

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