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There is an example of running and sold CPUs: GreenArray's GA144.

http://www.greenarraychips.com/home/documents/greg/PB001-100...

To quote: "Up to 96 billion operations per second" and "instanteous power ranges from 14 microwatts to 650 milliwatts"

Let's say there will be ten times less IPS (addition has O(log(WordSize)) delay in average case, for GA144 word size is less than 32, thus 10 times the reduction; fastest operation for 2-in-1 self-sync encoding is inverse which is just lines swap and does not incur any computation whatsoever) and at max power. It would be 650mW lasting for 1/9.610^9 seconds, or 6.810^-11 Joules or 68pJ (picojoules).

https://www.ics.forth.gr/carv/greenvm/files/tr450.pdf - page 28 lists power consumption of different operations. Simple integer includes addition and 32-bit variant is in range 50-to-80pJ. If we take average, it will be 65pJ which is very close to my worst-case analysis for GA144.

This means, in my opinion, that self-synchronous CPU exemplified by GA144 has efficiency at least that of synchronous ARM CPU, with very efficient sleep mode entry/exit.

GreenArray is a pretty special CPU and you can't compare green array ops with those of a regular CPU one on one.

Essentially it is a cluster of special purpose FORTH CPUs.

In fact, I can. I am comparing vaguely estimated cost of addition operation (thus worst case scenario for GA) against better known cost of addition operation on regular CPU.

To judge by anything on the record, you would think nobody at Intel has much love for anything asynchronous, but it's worth keeping in mind that Intel funded and later acquired a startup called Asynchronous Design Technology, later renamed Fulcrum Microsystems, to the tune of something like $100 million all together, and then let it slip under the radar. Last I checked its domain had been taken over by a tech blog. People from Intel have also usually put in an appearance at the IEEE Asynchronous conferences over the years. I'd venture to guess they know a thing or two about async at Intel but it's fine with them if the rest of us don't.

The prior name of Fulcrum Microsystems was Asynchronous Digital Design, not Design Technology. They fairly quickly decided that ADD was an unfortunate acronym...

I stand corrected. Thank you.

Fulcrum didn't slip under the radar, it was purchased by Intel in 2011[1]. Since then, Intel's switch and router division have had their part numbers start with "FM".

[1] https://newsroom.intel.com/news-releases/intel-to-acquire-fu... [2] https://www.intel.com/content/www/us/en/design/products-and-...

>Another Intel scientist (unfortunately I can't re-find that source) later said that the power savings of async CPUs aren't as high as claimed by their proponents.

Because of all modern chips that made with any consideration for power saving use clock and power gating

Gating is great when you have entire cores idle. Other than AVX2 units, does it save you any notable amount of power on active CPUs?

It can save you as much power as you want, nowadays OEMs simply type a number into registers and thats how much CPU will be allowed to consume.

Surely that answer is kind of how I imagine it might work for clock scaling, but not for gating, which I thought was more about turning on/off clock completely to various blocks that are not being used?

AVX-512 is gated, but causes heavy throttling.

> AVX-512 is gated, but causes heavy throttling.

In its current implemention, it does. Consider that this is Intel's first iteration of AVX-512 and don't forget that in its first iteration, also AVX was plagued by performance problems. These first iteration's main purpose is that "ordinary developers" (i.e. not only highly selected specialists that have to sign lots of Intel NDAs) can begin to develop and experiment with these new extensions. I believe that Intel has grand plans for AVX-512 and its next iteration will be the one that aims that "ordinary users" can profit performance-wise from applications that use AVX-512 instructions.

Not a lot of chips gain a lot from power gating though, due to various reasons.

Adding to my own post

> ... Apparently economically that didn't make sense for Intel because you'd have to re-create virtually a whole industry that is based on clocked chips.

Also you'd have to invent a sales/marketing scheme as an alternative to the existing one that is based on increasing clock rates. GHz is to the PC what HP (horsepower) is to the car. That might come to an end obviously but now at least we have cores.

going back to the car analogy, ghz is more like engine displacement or cylinders. they measure an implementation detail of an engine, not the output such as power (HP) or torque. I'd imagine that cpus will be compared on benchmark scores, which is already being done now.

> Also you'd have to invent a sales/marketing scheme as an alternative to the existing one that is based on increasing clock rates. GHz is to the PC what HP (horsepower) is to the car.

The GHz race has been over for a long time. Since Intel Core (and AMD Zen, I think; at least AMD Bulldozer had in my opinion a different design philosophy), it is all about smarter cores that do more in less clock steps. Also since AMD Zen, the "number of core race" has regained traction. Finally, in particular Intel tries to promote extra-wide SIMD instructions (AVX-512).

Just look at how they are promoting the new i9 (!) with 8 cores and 5 GHz :) https://thenextweb.com/plugged/2018/10/08/intels-9th-gen-pro...

Just use the average stage cycles per second, that's what we do.

That intel scientist was Shekhar Borkar

Thanks so much. That made me find the article:

"One of the biggest claims to fame for asynchronous logic is that it consumes less power due to the absence of a clock. Clock power is responsible for almost half the power of a chip in a modern design such as a high-performance microprocessor. If you get rid of the clock, then you save almost half the power. This argument might sound reasonable at a glance, but is flawed. If the same logic was asynchronous, then you have to create handshake signals, such as request and acknowledgment signals that propagate forward and backwards from the logic evaluation flow. These signals now become performance-critical, have higher capacitive load and have the same activity as the logic. Therefore, the power saving that you get by eliminating the clock signal gets offset by the power consumption in the handshake signals and the associated logic."

https://www.eetimes.com/document.asp?doc_id=1277174