Hacker News Reader

HNHacker News

Top New Best Ask Show Jobs

Comment by angelsl | Hacker News Reader

Parent Full thread

angelsl·

No, but this does it the way JavaScript wants it. FCVTZS has always been therr. FJCVTZS[1] is new.

[1]: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc....

Did someone say ARM is RISC?

View on HN

The traditional (eg mips) definition of risc was that the cpu should not hide how it operated - in essence, the compiler was required to schedule operations efficiently itself for both performance and correctness. That’s why MIPS and others have things like branch delay slots. It turns out that that is a terrible idea - it means binaries are tied to a specific micro architecture, let alone a separate implementation of the same ISA. Traditional risc also did not support floating point or integer division (both in software), except again software is necessarily slower than a hardware pipeline.

So risc has slowly become analogous to “more registers, orthogonal instruction set, not x86”

> Did someone say ARM is RISC?

Load/store are still always separate instructions, and instruction length is fixed — that's RISC enough. (But the distinction is not super meaningful these days anyway.)

Indeed, it could be said that ARM not being pure RISC is what keeps it competitive with x86. I wonder how long it'll be before x86 also gets a similar set of instructions...

The instruction is just specifying particular semantics, that doesn't really disqualify it from being RISC. The instruction doesn't do more than the baseline variant.

Reply on news.ycombinator.com