The hard part AFAICT, is the modeling of the chip for timing analysis. Whereas all of the timing information is explicitly defined for programmers on CPUs, that timing information (and the models of how FPGAs are binned) is extremely proprietary for FPGA vendors, to the point of being treated as a trade secret. Since they use custom cell layouts, I've heard that they consider the timing information core to their IP. If another vendor got them, the could conceivably see what interesting points are optimized past a foundary's standard cells because of the tighter timing guarantees than they might should have.

Now, I'm personally of the opinion that their competitors have taken their chips into one of those nifty 3d xrays and know the exact layout of the cells anyway, but it's hard to push that idea.