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Comment by 40acres | Hacker News Reader

Disclosure: I work for Intel.

As far as I can tell nanometer is basically a marketing term now and will not be as important to performance as it has been in the past. Not only is there not a standard for what constitutes a Xnm chip these days (Intel, TSMC & Samsung all have different descriptions) but chips in the future will be heterogeneous in which features are a specific nanometer size. It's getting so expensive to reduce nanometer size that the next generation of products will have some 5 nanometer features, some 10 nanometer features, and some 7 nanometer features.

Chip packaging technology, power performance and advanced fabrication techniques (ex. EMIB, stacked die, EUV, die disaggregation) will decide who has the most performant chips from now on, not feature size.

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More people need to understand this. The “<x>nm” nomenclature now represnts the new generation of product. Similar to how 4G cellular is not 33% better then 3G. It just means the next generation.

One of the things that got Intel in trouble with their 10nm generation of products was that their 10nm process was much more ambitious then other companies. Turned out that it increased the complexity (and decreased the yield) so much that they were not able to make it work when they expected to.

There are also process generations within the same process "size". Intel has 14mm, 14nm+, 14nm++, and now 10nm (the limited # of 10nm skus released so far is because of all the 10nm problems) and 10nm+. I thought I read somewhere that while 10nm+ was originally intended for Ice Lake and beyond, they're considering moving some 10nm products to 10nm+ early because the original 10nm process yields are so awful.

The 3g/4g analogy works here too. LTE has categories (0 to 19, with some extras) that increase bandwidth (or another metric) from Rel8 to Rel13.

Please could we not use this 3G / 4G analogy?

1. 4G, or LTE really is at least 33% better than 3G even when it initially launch. Just the latency reduction were huge improvement.

2 The different between baseline 4G and top end 4G is an completely different scale to nomenclature.

I'm sorry, I don't understand why it isn't a good analogy.

The comment is saying that nanometers really only denote the technology generation, and that is exactly what 3G and 4G denote.

There is wide variation between 4G phones, as there is wide variation in 10nm processes. The analogy seems ideal.

I think the point was that 3G -> 4G does not imply a literal 33% increase in performance, which one could guess was the case as 4 is a 33% increase over 3 (3x1.33333~=4)

I always thought it just meant "fourth generation". Never until now did I think 4G would be a 33% increase over 3G

I don't understand why. Could you elaborate more? Isn't the whole point of reducing the minimum feature size to increase the number of transistors that you can pack in a layout or in other words the smaller the node, the more density you get and therefore more processing power with less energy consumption? How is that not supposed to impact performance?

You're correct, smaller features will improve performance. What I'm saying is that it is becoming so expensive and difficult to get high yield on smaller feature size that from a product generation to product generation other performance features (like the ones I mentioned before) will be the main factor to improved performance.

You can see this with Intel right now: CannonLake (10nm) has been delayed due to yield issues but KabyLake, Coffee Lake & Whiskey Lake (14nm) are all improvements over the original 14nm product (Skylake).

The gist of what's being said on this post and the thread on Apple's video is that everyone is generally around the same size for various features. So we might get marketing speak that we're on "10nm" or "7nm" or "5nm", but that doesn't correlate to much. Just like "4G" and "5G" technically mean something, that doesn't mean the carrier offers speeds remotely close to the specification they say they provide.

Features lists generally include the transistor gate pitch, interconnect pitch, transistor fin pitch, and transistor fin height. None of these features are actually "10nm" or "7nm, but range anywhere between 30nm-60nm. Although sources are conflicting online, it looks like Intel 10nm is about on par with TSMC 7nm. Some features for Intel's 10nm are larger, while others are smaller than TSMC 7nm. Also _most_ sites are saying Intel 10nm has a higher transistor density, but information is kind of flaky on this metric.

The way I understand, it’s really more like minimum feature size (like think a trace/wire and not a transistor). So it’s more like a sort of DPI measurement

Or like CPU clock speeds, which have never correlated directly with performance across families, even when comparing something as old as the 6502 vs. Z80.

It's not quite the same thing, since CPU clock speeds do in fact have a well-defined meaning.

It's starting to get murky. We're back to the point where not everything runs at the same speed (take AVX for example [0]). Add to that that some of the frequencies are turbo, and specific frequencies are only achieved under very specific load conditions, etc.

You get something that physically is very clearly defined but in practice it's not. Just like the minimum feature size which doesn't tell you much about the rest of the transistor. Perhaps if they used an average feature size it would make more sense for the regular person.

So how are the fabrication sizes different from the frequency that gets advertised on the box? "Oh that? It's only when you load one core. And don't run anything using these specific instructions. And when the temperature isn't too high. And...".

[0] https://www.tcm.phy.cam.ac.uk/~mjr/IT/clocks.html

Yea but TSMC's "7nm" is definitely smaller than Intel's "14nm"(+++), which is what Intel is actually on right now, and will be for at least another year.

What's funny about this still though is that people keep saying TSMC's 7nm is roughly equivalent to Intel's 10nm like that somehow scores points for Intel... even though Intel hasn't been able to ship their 10nm process for shit.

So no matter how you slice it Intel has fallen behind.

A few generations ago they just stopped being able to reduce minimum feature size. Instead they're working on some kind of hypothetical combination of work-per-watt and transistors-per-centimeter, ignoring additional layers.

Do you have a source that backs this up? I am under the impression that 7nm is a marketing term but that it is still smaller than the previous node.

Yea that's all true. The problem is consistently defining what exactly constitutes a 'feature'. Intel's 10nm features are smaller than Intel's 13nm features but it's harder to compare Intel 10nm to other companies' 10nm processes.

Or at least that's how I understand it. At the end of the day the chips are now physcially small enough to do whatever we want so it's more useful to directly compare power consumption rather than the implementation details. After all, if a 10nm Intel chip can give you the same output per joule and per second as a 7nm Apple chip, does it really matter how big the transistors are?

I don't disagree with you. Hell I have no basis to do so.

But this sounds soooo much like the marketing around the IBM/Moto G3/G4 chips that it's amazing.

"This specific number is bigger in the competition, but the number that really matters is this other one that's smaller!"

And this was legitimately true for a certain amount of time. There were G3 and G4 chips that actually smoked Intel's best chips in the mid-late 90s and early 2000s.

This is probably true as well. I have no reason to think otherwise.

But I love how you're sheepishly trying to make a win out of different numbers it's doing. Tastes like justice for those of us who were a little chafed by other CPU fabs not quite getting it right for a while, 20-something years ago.

Totally understand your point. I think the main thing I'm trying to achieve with my comment is that consumers should understand that the reported feature size will correlate weaker in the future to overall performance than it used to. Nanometer is still the preferred marketing feature of choice but there is a large class of innovative techniques that are maturing the semiconductor fabrication space right now that are going to contribute more and more to the real world performance than feature size.

As feature size shrinks new fabs will need to be created to support the manufacturing, a Fab is a multi billion dollar investment. Eventually the industry will have to choose if feature size is something we will continue to push in favor of investment in other techniques.

I'm curious as to what the job title and pay range for the, what I assume to be EE's, designing chipsets make at an Intel/Apple?

There are many roles. From soc architects to ASIC design engineers, verification folks at all levels, analog folks, physical design folks (layout, etc), circuit designers. It takes a village. Degree-wise mostly computer engineering, electrical engineering, and computer science. But I mostly know the cpu space. On something like a phone/watch there are also all the sensors, camera stuff, etc. No idea where that all comes from.

I'm CoE and have done some FPGA in school. Stuff is pretty interesting.

Maybe this explanation is simply too long, but how is this? Isn’t this simply a measurement of size?

As a layman, I see how Retina can be a buzzword, but not 7nm vs 5nm.

> Isn’t this simply a measurement of size?

But what are you measuring? "Minimum feature size" is cited often.. what constitutes a feature?

I think this is where the line is blurred.

Couldn't they use use sqrt of transistors per area?

That's actually what Intel is trying to push instead of feature size.

Does the small wire size make the iPhone more susceptible to drop shock impact?

It has nothing to do with the size of any wires. The chip itself is a solid wafer of silicon with a tiny bit of copper, aluminum, etc deposited on top. It's all one solid piece though, the silicon die itself is never going to be damaged from shock unless it's strong enough to break it in half which isn't going to happen before the rest of the device is toast.

There's tiny bond wires that connect the silicon die to the pins on the outside of the chip but that has nothing to do with the process size of the chip. Basically the feature size just means that somewhere on the die there's a tiny spot 7 nm wide. It's a measure of how fine they can get it when etching and doping a silicon wafer.

"Basically the feature size just means that somewhere on the die there's a tiny spot 7 nm wide." Understood. And these tiny spots are not brittle you say. Presumably because of embedding?

It's sort of like measuring the wood grain of a log. The wafer is solid but the wells are measurable, just like the log is solid but the grain can be measured.

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