Intel can’t supply 14nm Xeons, HPE recommends AMD Epyc
semiaccurate.com
semiaccurate.com
Looking back at other submissions from that site ( https://news.ycombinator.com/from?site=semiaccurate.com ) it appears many HN readers are too. Based (only) on the submissions, it looks a bit like an AMD fan site.
Are you willing and able to elaborate?
https://www.semiaccurate.com/fullyaccurate/
Some things since then, they were the first media outlet to talk about how Intel's 10nm was a disaster, The first media outlet to talk about Zen chiplet technology and predict AMD had a homerun on their hands.
AMD used to be quite popular in the Athlon era, especially when Intel screwed up big time with Pentium 4 and Itanium. But, as we know, Intel recovered, then used anti-competitive tactics against AMD, and finally AMD screwed-up with its next architecture. All of these more than ensured Intel's comeback.
So I'd say wait until AMD has 50% of the market (not just the custom PC market, which AMD will probably have within 2-3 years) to feel sorry for Intel and worry about Intel dying.
Then... Core2Duo happened so fast and AMD disappeared so quickly. Felt like overnight.
No, am still worried about Intel plotting behind the scenes to undermine AMD. AMD is nowhere near the position to abuse their power and they're unlikely to be for a long time, so let's not be alarmist here.
However, I don’t think this is really a major worry, because the actual real threat is from ARM and ARM has a lot of manufacturers.
My takeaway from this is that server manufacturers are starting to recommend Epyc is a solution which will increase AMD's market share. This will just create more competition between Red and Blue which will give consumers faster innovation and better prices.
Because Intel's 10nm process is delayed, their 14nm fab is overbooked leading to a chip shortage.
Two fabs output more chips than one fab. Intel has deals with other companies for both 10nm and 14nm production and some of those deals are undoubtedly based on Intel moving their own chips to 10nm. At capacity and unable to increase as expected means customers move to other companies that make compatible, competitive products. Once those companies move, they may not come back.
This is quite a bad position to be in.
We need competition in the FPGA space again.
https://www.tomshardware.com/news/14nm-processor-intel-short...
> That ramp is occurring as Intel is also bringing production of its 14nm XMM 7560 modems online for Apple during the second half of this year. The new Apple contract, which consists of millions of modems for iPhones, will certainly be a top priority at Intel's fabs.
Assuming this to be so, Apple may not be allocated the highest priority.
Not the same as when a manufacturer says they’re making as many as possible and they’re selling out.
I understood that TSMC would be manufacturing the next round of AMD processors, since Global Foundaries didn't have 7nm ready.
Intel's recent 300-series chipset refresh found its new chipsets coming to market with the 14nm process, which is necessary to meet California's new power standards.
Intel's XCC die is 694mm^2 for a 28-core, while Zen / Zeppelin is 213mm^2 for an 8-core. Intel's XCC 28 core is around 25mm^2 per core, while AMD's Zen is 26.6mm^2 per core... suggesting a slight advantage to Intel!
Furthermore: Intel's XCC die has 28-cores. When defects come into XCC, Intel can simply disable those cores and sell them for cheaper. For example, Intel's Xeon Platinum 8160 is a 24-core. Presumably, 4-cores are defective but Intel can still sell it for $5000 or so.
So a defective product would require a manufacturing defect somewhere critical. But individual cores can most certainly be disabled during the manufacturing process and sold as a lower tier product, like the Xeon Platinum 8160
As such, Intel definitely has good yields, at least on 14nm production.
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The main advantage is that AMD's strategy works way better when yields are poor due to a new process being not fully understood. But as defect rates drop, Intel's monolithic strategy seems to have slight advantages over AMD's. (Remember: Intel's cores are slightly superior in IPC, have slightly faster caches, and AVX512 enabled).
AMD's strategy is definitely good, but I don't think Intel is really that far behind.
And I wouldn't be surprised more customer are looking at EPYC anyway, every microcode update from Intel has resulted in % of performance lost, at this rate we will be back to Broadwell era soon.
Microcontrollers are all backlogged, chip capacitors are also backlogged. PCB Fabs are backlogged, assembly houses at least in the US are at capacity.
What I suspect is demand for electronic 'things' by poor people in China, India, and Africa are outstripping supply chains across the board.
“Rock's law or Moore's second law, named for Arthur Rock or Gordon Moore, says that the cost of a semiconductor chip fabrication plant doubles every four years“ https://en.m.wikipedia.org/wiki/Moore%27s_second_law
Maybe instead of virtual machines we'll end up running (some) workloads on cheap, low power and isolated ARM CPUs, directly on bare metal without potentially leaky virtualization. Something like 4-16 GB of ECC RAM over 1-2 channels, quad core Cortex A73, A76 or similar.
(Some ARMv8 designs are actually not that far behind of x86 chips in scalar performance anymore. SIMD (vector integer/floating point) is another matter, but I guess it's not impossible to slap a few 256 or 512 bits wide SIMD units in ARM designs.)
With a completely free competitor in risc-v, and not much market penetration, what is the motivation for a customer to pay the licensing fees?
Only for applications whose workload can be parallelised. Many applications remain single-threaded, and until a parallel version is developed for all these applications, single thread speeds will matter.
Just that this time, these pastures are at Intel, so who knows what'll happen?
Rumor is that she's somehow related to NVidia's chief. Like 2nd cousins or 3rd niece / something-something removed or something of that nature. Just for some delicious irony.
EDIT: Found it. Jen-Hsun Huang is apparently her Uncle. https://babeltechreviews.com/nvidias-ceo-is-the-uncle-of-amd...
> Technically, Lisa Su’s grandfather is Jen-Hsun Huang’s uncle. They are not exactly niece and uncle, but close relatives.
DL385 is your workhorse platform. DL325 is a 1P design based for heavy PCIe connected (read: NVMe) devices.
The CL3150 is a cloudline server and will likely be more consumed in the service provider space, in my opinion.
The Apollo 35 is available to top 200 volume accounts (which has been annouced publicly, but is not available to your everyday customer.)
This type [of information leak] is my worst nightmare as someone who works with resellers, letting these types of documents in the wrong hands or somehow access is breached like this.
Edit 2: I am a server SA, MASE. I configure servers all the time. If customer demand shows the swap, you could see the proc move over to other lines, such as blades and the HPC markets.
Maybe we'll see some Silicon Graphics branded HP gear too?
Depending on your SGI server, the name may have gone into the appropriate HPE family name.
If you need help with our new decoder ring, I'd be happy to point you in the right direction.
I expect HPC workloads to take advantage of AMD chips, but I do expect many of the mathematical improvements that the Skylake instruction set provides to amplify desire in the computational HPC/numerical computation/ non-GPU stuff.
Also, do you expect 7mm EPYC to do well in your space? Thanks!
They are cheaper due to fabrication process. The PCIe lane story is stuff of fanboys. It comes at a cost, power and heat.
Secondly, anyone looking at an NVMe box should be looking at AMD in my opinion. The trick is if you are doing a VM farm, mixing Intel and AMD aint the best idea, as you all know.
I see EPYC ticking up fast.
In terms of exploits like Spectre/Meltdown, I'm pretty sure the exploits AMD claimed were not vulnerable, they ended up pushing out microcode for anyway. So its a moot point.
I HAVE come across alot of customers who have DOUBLED their core count due to Spectre/Meltdown mitigations, and they are attracted to AMDs, high core, lower cost options. But remember, the power draw is different and always test/PoC!
Could you unpack this a bit? Specifically, I'm curious if the cost is a premium per lane (e.g. W/lane greater on AMD than on Intel) [1]. Also, is that cost at all affected by the I/O volume or merely the CPU being power-hungry overall?
[1] Of course, that assumes everything else being equal, which it can't be, as well as equal proprotion of PCIe utilization, which is unlikely.
PCIe lanes and counting them is funny math. Do the homework on system boards, how they communicate, and the tax of moving information between processors.
However, I would say their tests were short, and AMD processors have 3 power operating modes. There was also a neat blog posted somewhere (I think on here...) a little while back suggesting that the AMD proc did not need to run at advertised power on the customer procs. It was about compile times and how much power still resulted in good times. That was consumer-grade Ryzen chips tested though.
> On paper, you get more lanes at a lower TDP w/ AMD.
I was hoping you (or anyone) had at least some real-world anecdata.
However, the theoretical power cost being lower suggests it's unlikely that if there's a premium in practice, it's unlikely to be significant.
> PCIe lanes and counting them is funny math. Do the homework on system boards
It's not that funny. Latency "taxes" are certainly a concern for some workloads, but, ultimately, if there's not enough bandwidth to get the data to the CPU, such that it might end up idle, that can trump any tax. The difference between 40 and 128 lanes of PCIe 3.0 in transferring 64MiB is on the order of 1ms.
Finding a mobo that allows access to all the lanes might be more challenging when there are 128 than when there are 40-48, but I expect the popularity of NVMe to reduce that challenge somewhat.
OTOH, it seems Epyc uses half those lanes for communication between CPUs, so the usable lanes doesn't go up for 2S vs 1S, so perhaps the comparison is really 128 lanes vs 96 lanes.
Do you have a "relevant" chunk of customers that are really looking for the high-density PCI-Express connectivity? Are the 128 lanes per system a feature that actually draws in users with real world demands or is this the wrong thing to focus on?
> There was also a neat blog posted somewhere
You must be talking about the DragonflyBSD mailing list: http://lists.dragonflybsd.org/pipermail/users/2018-September... (as linked by others by now).
To me this wasn't very surprising. It's well understood in the more technically inclined enthusiast community that underclocking Ryzen yields tremendous efficiency improvements. Famous overclocker "The Stilt" did a great analysis on Ryzen's launch day in 2017: https://forums.anandtech.com/threads/ryzen-strictly-technica... One of his benchmarks showed an almost 80% efficiency improvement when underclocking an R7 1800X to 3.3GHz, which is just above Epyc's maximum boost frequency. Since Epyc is almost the same silicon as Ryzen 1st Gen (B2 stepping instead of B1), the chips should have almost identical characteristics.
Unfortunately, I'm not aware of any similar detailed analyses on recent Intel Core processors to compare. Samsung's low-power manufacturing node used by AMD has often been cited as the specific reason for the steep efficiency curve (and the realtively low upper end compared to Intel), but the general trend is the same for almost all chips.
On the other end of the spectrum, overclocker der8auer measured about 500W draw in Cinebench when overclocking the Epyc 7601 to around 4GHz: https://redd.it/92u6db
I'm going to go out on a limb and suggest (based on my own experience[1]) that most users are too ignorant to know that this might be something that they want or would benefit from.
Some of us have always demanded more I/O bandwidth (even if it meant 4S servers), but typically with a price limit.
I do, however, suspect that additional demand could materialize in the form of NVMe slot count.
[1] particularly with so many potential employers being categorically cloud-only, they don't even want to know about the underlying hardware or what it's capable of.
But even in the scenario where the microcode actually did incorporate some "interesting" changes, they haven't impacted performance at all. So this is basically the world's biggest ever design win at this exact moment.
HPE, along with all other server vendors, is starting to see supply constraints on various Intel Xeon-SP processors—commonly referred to as Skylake—used in our Gen10 servers.
–Intel is supply tight on Skylake SP HCC, Skylake SP LCC, Skylake SP XCC, and Skylake W LCC processor series.
–Customer demand for various Skylake server processors is exceeding short-term supply.
–Intel is working diligently to increase supply but indicates limited ability to materially improve Skylake availability potentially through December 2018.
What sorts of evaluation opportunities do you provide for Intel vs AMD processor comparison?
Besides short-term on-site placement, this could even look like remote access to a specifically-provisioned lab environment.
Something like this would be pretty cool to evaluate a wide range of processor/memory/storage/etc combinations.
I'm absolutely sure this almost certainly exists but I thought it would be interesting know how it actually works. (I'm not in the server hardware industry, but am very interested in how it works)
https://www.amd.com/en/campaigns/amd-and-dell
https://www.dell.com/support/article/us/en/04/qna44314/dell-...
https://blog.dellemc.com/en-us/poweredge-servers-amd-epyc-pr...
http://www.itpro.co.uk/server-storage/30799/dell-emc-powered...
Personally, I've never been convinced that such high server densities [1] provide a net benefit. Ever since "blade" systems first came out, and through the current availability of the half-U models (e.g. 4 per 2U) or even 2S 1U models, they've been plagued with thermal design issues and, sometimes, reliability issues due to non-commodity parts and/or needing to spin tiny-diameter cooling fans so much faster.
Until relatively recently, there wasn't even datacenter space available that could accomodate such systems at full density running at full load. What did become available was at a premium (in addition to paying a premium for the higher-density hardware in the first place).
[1] more than 1S/U or so
It's entirely possible this was deliberate but I call it unlikely.
Oh please.