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Comment by crawshaw | Hacker News Reader

It would be wonderful to simplify CPUs and ship this work off to the compiler. The two difficulties I see are:

Firstly, every microarchitecture will have a different optimal schedule. This means a significant shift in how binaries are deployed. Either the compiler is built into a distribution system aware of microarchitectures (for example, bitcode and the Apple App Store), or these tasks are brought online with a JIT compiler. For the sake of software freedom I hope for the latter.

Secondly, this paper shows 88% of the speedup is static. That means there will always be a little extra speed available to a chip maker that ships an OOO processor. For the same dollars, will you take the CPU that is 10% slower. Today in the middle of Intel's security disaster, sure. But ten years from now when CPU security is stable again, that free 10% performance will be compelling.

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It's not free though. If you can actually remove most of the power/area hungry ooo scheduling logic for only 10% less performance on real world workload, you can pack a lot more cores or a bigger GPU on the same chip without blowing up TDP or die size.

Sure, some use case will always require the highest single thread perf at all cost but that's less and less true these days.

The speculation must be done with content-addressable memory, because you must commit or rollback register mapping after speculative execution have succeed or failed.

The dynamism, on the other hand, is a way to issue (possibly) out of order commands when they are ready to be executed (their inputs are ready and no write conflicts detected). For this you need a scoreboard (which is also needed for speculative execution). Scoreboards are for registers (which one is ready, etc) and for commands (which one is eligible for execution). As you can easily assume, these scoreboards are bit vectors, not some interesting thing that maps 80 internal registers to 16 externally accessible register indices.

The scoreboarding in CPUs have long history. They were used in Burroughs' CPUs long ago. They were used in early Alpha AXP designs (first one or two, I guess). They are very easy to implement - yours truly is guilty in this, having done that in month and he is not even a hardware designer.

From the paper: "we make no attempt to describe the mechanisms that would be necessary to produce these schedules nor the architectural fea- tures that would be necessary to encode these schedules. We do, however, think that a useful mental model for the system under study is a machine like the Transmeta Crusoe [9], which consisted of a VLIW processor coupled with the CMS dynamic binary trans- lator. Our study can be viewed as investigating the potential for a futuristic dynamic optimizer provided it was not constrained in the static schedules it could generate and it could effectively profile the execution so as to generate relevant schedules."

"The Itanium approach ... was supposed to be so terrific—until it turned out that the wished-for compilers were basically impossible to write." - Donald Knuth

I should have qualified my post with the assumption that such a compiler could be written. I don't know if it could. I suspect, if a compiler was focused on one specific micro-architecture rather than a general ISA, that it could.

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