Your only comments on HN seem to be to criticize RISC-V.

The posters intention is not to start producing hardware, at no point does his project mention taping it out and manufacturing. Obviously it is just a fun side project to implement the RISC-V core ISA in an FGA. It was then made open-source on GitHub so anyone else interested can look at it. Chill out mate.

> Writing RTL takes one night but, how long will the verification take?

Obviously more than a night, but hey development is completely open so you can see for yourself.

> How much will it take to tapeout?

0 days. It is running on an FPGA.

> Who will pay for it?

See previous comment. Presumably the author paid for the FPGA, but maybe it was a gift?

As someone living in hardware land, I have a lot of respect for all the effort that goes into those steps of the process and I’m glad you brought it up, but presumably they aren’t that important to the point of a hobby project like this.

After two weeks, I hope most critical problems are already solved, as long more complex software is working without problems, thanks to the clear and simple RV32I instruction set! Of course, as observed in the project description, I am working only with FPGAs, which means that is far more faster and easy to simulate with real software and find problems. As long most of complex work is done by the FPGA tool and I have a well comported clock environment, always according to the specifications, the verification is purely logical.