Intel delays 10nm Cannon Lake processors, again, until late 2019

They're both process nodes, with certain minor-ish differences here and there. TSMC calls theirs 7 nm, Intel calls theirs 10 nm.

Their performance characteristics might be around the same. In practice... who knows. We do know that Intel's current 10 nm CPUs are pretty much broken ~ best they could currently do was useless laptop-grade 2.5 GHz dual-core with no functional iGPU. Not sure about the HT, though.

But who can predict what will happen...

Yes, intel's 10nm absolutely smashes Samsung, GF and TSMC's 10nm processes. Yes Intel's 10nm should be very competitive/comparable with Samsung/GF/TSMC's 7nm processes. But all of the Intel 10nm metrics are slightly worse than the 7nm processes its now competing with.

To cherrypick one metric as an example -

  * TSMC 10nm sram bitcell size: 0.042 µm²  
  * Intel 10nm sram bitcell size: 0.031 µm²  
  * TSMC 7nm sram bitcell size: 0.027 µm²

So there is a leap coming for Intel as well if they go that route, and after the massive success of Ryzen, they are likely going there. Just easier to scale core counts if you can use smaller dies and just use a lot of them with an interconnect fabric.

Of course, Intel also appears to be forgetting that they have the ultimate advantage in getting to accelerators--they can dump the accelerator in the same socket, Nvidia can't--since they keep trying to compete by using expansion cards despite that being the worst limiting factor for offload.

Intel's current architecture is just small incremental improvements to a 27 year old design. The biggest features they have added are Nehalem's hyperthreadding (which they borrowed from Pentium 4) and Sandybridge's uop cache (loop cache).

All their other performance improvements have come from small micro-optimisations and just chucking transistors at the design. Better branch prediction, better load/store buffers, more load/store buffers, more execution units, bigger reorder buffers, wider instruction decoders, more renaming registers, wider instruction retirement, more unique/specialised instructions and of course, clock speed improvements. But it's still fundamentally the same design which intel could have done back in 1991 if they had the silicon budget.

And this was absolutely the right design decision, everyone else is copying the same design. Apple copied it with their Cyclone/Typhoon/Twister arm CPUs. ARM copied it with their Cortex A57, A72, A73 cpus. AMD copied it with their Zen architecture (after trying out new ideas with Bulldozer and failing). IBM and Sun/Oracle have server class CPUs with more or less the same ideas, but 4 to 8 way "hyperthreadding".

AMD's Zen might pull ahead slightly, but that's only because their design is newer and hopefully free of cobwebs than Intel's design.

But there are still plenty of new CPU design ideas out there, It's quite possible we will see another 50% jump in single threaded performance.