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Comment by nordsieck | Hacker News Reader

Case in point:

> chips will support up to 3.84 TB of memory per socket ... due to combining 512 GB Optane DIMMs and 128GB DDR4 DIMMs

> ...

> in a 6 x Optane and 6 x DDR4 configuration, they will provide 3072 GB of 3D XPoint memory and 768 GB of DDR4 RAM for a total of 3.84 TB of memory

Optane DIMMs don't really have the performance characteristics of traditional DRAM. It sounds like the real capacity per socket is 12 x 128GB = 1.53 GB, which is the same capacity as the previous generation.

That being said, I'm optimistic about Optane DIMMs - it seems like an interesting performance point in between DRAM and SSDs.

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Tiny correction: Should be 1.53 TB, not 1.53 GB

Certainly not tiny, off by 32 bit

Tiny correction: Should be 10 bits not 32 bits.

I meant tiny as in maybe not even worth pointing out since people will understand it anyway.

only 3 bit diff between the strings

Even tinier correction: it's exactly 1.5 TB (1536/1024).

Yeah, marketing lies. Go AMD go!

AMD is guilty of it as well. "AVX2" -> not really! But yes I do wish them well. Make the avx support real AMD!

As far as I know, Ryzen has avx-256, its four 128bit units can join as two 256 bit ones without any penalty.

What makes this not real AVX? Because there is not one dedicated 256-bit unit?

> without any penalty.

My understanding is that without any penalty was not true, but it is possible the new gen cpus have changed that, I have not firsthand benchmarked it.

> without any penalty

Except literally running at half capacity. That doesn't qualify as a "penalty" to you?

The point was that AMD advertised support for AVX in a context where you'd expect it to be performance-comparable, and what they shipped was "support" for AVX in the sense that the code wouldn't crash, but wouldn't provide any performance benefit over SSE either.

oh, they are twisting words with the marketing about "no penalty" pretty bad!

https://en.wikichip.org/wiki/intel/frequency_behavior

Intel reduces clockspeeds when running AVX2 and drastically decreases clockspeeds when running AVX512. AMD's slightly smaller unit doesn't need to slow down, so the actual performance difference is smaller than it would appear.

Changing frequency takes time. Also, if you are putting through an AVX instruction and a few integer instructions at the same time, the integer instructions will downclock the whole time the AVX pipeline is in use (plus the time before/and after while the clockspeed is being adjusted) decreasing performance for more than just the AVX.

There are a couple articles written on the topic. Here's one.

https://blog.cloudflare.com/on-the-dangers-of-intels-frequen...

https://software.intel.com/en-us/forums/intel-isa-extensions...

> Except literally running at half capacity.

I’ve been writing SIMD code for some time now, and I disagree.

You can read the documentation I’ve generated https://github.com/Const-me/IntelIntrinsics AVX intrinsics begin with _mm256_.

You’ll find that for some AVX operations, such as _mm256_fmadd_ps, _mm256_adds_epi8, _mm256_blendv_ps, both latency and throughput of Ryzen is equivalent to Skylake. For some others, e.g. _mm256_add_ps, _mm256_mul_ps, Ryzen is close to some older Intel, Haswell or Broadwell. Only for very rarely used stuff, e.g. _mm256_broadcast_ps, _mm256_madd_epi16, Ryzen is significantly slower than Intel.

AVX2 is a set of instructions and AMD supports them. How they support them is a different question. Does Intel not support AVX512 because their processors run at a lower clockspeed when they execute? There are more and less efficient ways to support an instruction set.

AMD decided that consistent clockspeeds were more important than wider units. They decided that most users won't use enough AVX instructions to overwhelm the AVX unit (especially with consistent clocks), so there was no justification in ballooning the die size and increasing power consumption without a decent payoff.

https://en.wikipedia.org/wiki/Advanced_Vector_Extensions#New...

Well at least it can address 3.84 TB of RAM (maybe more, because that's not a multiple of a power of two.) I suppose if you could get 256GB DDR4 DIMMs you'd have 12*256 = 3072 = 3TB of RAM. Yuu'd have to give the RAM cartel your first-born to pay for it, but that would be some machine!

But what market are they even trying to hit here? DDR4 prices are insane, but home consumers don't run large NUMA systems.

Data center admins are going to be able to get the capitol for real DDR4 over Optane. They'd need to be ordering a lot of servers before the price point becomes significant enough that they'd order an Optane configuration and decide to benchmark them.

I'd be curious about the real benchmarking at that point. It there a performance boost to simply have more memory, even if some of it is Optane, or is it better to have a lower capacity without the Optane sticks? I have a feeling this will vary heavily by application too.

> It there a performance boost to simply have more memory, even if some of it is Optane, or is it better to have a lower capacity without the Optane sticks?

I would imagine it depends entirely on whether your working set fits in main memory already. if yes, you're not gonna get much speedup from more memory. but if you have to keep swapping from a traditional SSD, it's gonna be hard for faster main memory to make up for that.

I thought the real advantage of Optane was bypassing the pcie bus, with much larger bandwidth of dimm: 80GB/s instead of 12GB/s

DDR4 dimm read throughput is about 20GB/s per dimm. PCIe 3.1 x4 is 16GB/s. I feel very comfortable claiming that these optane dimms will not reach 20GB/s of sustained performance.

The advantage here being latency (and thus single queue throughput)

But pcie bus is shared with other cards. So 8 dimms is 8x faster than 8 pcie cards.

> But pcie bus is shared with other cards.

No, it's not, that's the whole point of pcie, and dimms share the memory bus anyway, so the whole point is moot.

Hmm. In that case never mind.

Well, it depends. "True" pcie slots do not share the bandwidth, but depending on available CPU lanes, which is awfully few in the last years on Intel - 16 lanes in top of the line i7? thats one graphics card - the slots are switched to 8x/8x, 8x/4x/4x and so on when populated.

M.2 slots are a whole another story, they are usually connected to the chipset instead of CPU on desktop motherboards (and finding this information for any particular board is difficult). The chipset is connected with CPU through DMI, which equals to pcie 4x and this is shared with everything on chipset - satas, gigabit ethernet, usb 3...

> PCIe 3.1 x4 is 16GB/s

PCIe x4 is 3.94GB/s. PCIe x16 is 15.76GB/s.

> DDR4 dimm read throughput is about 20GB/s per dimm

Per channel, not per dimm. Two dimms typically go into a singular channel.

> The advantage here being latency (and thus single queue throughput)

Agreed

The idea of putting ssds in memory dimms isn't new, the jedec standard for this is included in ddr3. It's referred to as an nvdimm(-f for SSD), sandisk and IBM both produced and sold them. These are supported since Linux kernel 4.1 and show up as a block device in /dev/pmem. The latest optane variants are nvdimm-p and are not treated like block storage devices but instead as persistent memory to the OS.

The storage dimms have some notable benefits over pcie nvme ssds - latency to the processor is extremely low, they give extra total storage I/O since they're leveraging a different controller on the cpu with its own bandwidth, while still leaving pcie bandwidth for traditional storage. They can add capacity to a small system (a 1U server can hold 24 such ssds)

As I see it though, these optane dimms are just fast swap drives which do not offer the same consistent throughput as true memory dimms. They are transparent to the OS which is normally in charge of deciding what stays in memory and what goes to swap. Use of an Intel sdk is required to leverage much of the benefits. It's also Intel-only as far as support goes for now. As usual the marketing doesn't mention the throughput or pricing and instead of comparing to memory they compare it to storage.

http://www.admin-magazine.com/HPC/Articles/NVDIMM-Persistent...

https://thessdguy.com/an-nvdimm-primer-part-1-of-2/

https://www.extremetech.com/extreme/270270-intel-announces-n...

Intel keep positioning optane as "close to dram" preformance (especially with misleading marketing nonsense like this), it does have some advantages over flash, mostly related to random access times, but its nowhere near the orders of magnitude more preformant that something would require to fill the preformance point between DRAM and SSDs.

Optane is almost entirely hype, with no substance.

> Optane is almost entirely hype, with no substance.

As it has been from the very first announcement. Intel is being very misleading marketing Xpoint as "memory". It's not even saying it's "close to memory" now. They're literally calling Xpoint memory (as in the same meaning we use for RAM).

Considering Xpoint has much lower performance than RAM, I'm starting to believe that maybe the FTC should intervene over "false advertising". It's just too bad the U.S. doesn't have as strong laws as Europe does for false advertising.

I don't see how a first generation product with similar performance and superior latency to a mature technology (nand) that took decades to develop has no substance. The second generation of Optane is coming out this year and it's going to be an order of magnitude better. It's just a matter of time until nand is obsolete.

If Optane is Intel-only, it is not going to replace NAND.

You and mtgx both mention Optane performance is "not even close to dram." I'm interested in if you have found anyone who has benchmarked the DIMM version with respect to actual DRAM. I see several sites that have benchmarked the Nvme version but this has additional hoops that the DIMM version would not have to jump through and so I've been on the lookout from Anandtech or another reputable source for actual numbers.

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