Ask HN: Who's writing Verilog/VHDL, and what are you writing with it?

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Recently I've been relearning Verilog with an FPGA. It's a lot of fun for me, but I've never written for hardware professionally and I'm curious about those of you out there who are.

For those of you who use an HDL on a daily basis, what are you writing? What's the project? What industry? What are your tools/stack?

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I work for a small trading firm. Our trading platform is on FPGA. I use SystemVerilog for both RTL and testbenches. I edit in Sublime with a SystemVerilog plugin. I use Sublime's build system to call Modelsim/Questa commands to catch errors inline. I run sims in Questa. I build with Jenkins calling Vivado Tcl scripts and use Perl to scrape the logs and timing reports to determine if a build was successful.

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