Using Records in VHDL

As someone who is trying to learn VHDL I really appreciated the well written article. Looked through the site to see if there were more guides I could learn from and found that this is your first. Looking forward to more content.

I see that you just started the blog, I wanted to add you to my RSS reader but there's no RSS, simple suggestion :) Great article otherwise.

Records are really great in theory but I have usually found difficult in practice. Mixing them with Verilog or SystemVerilog sometimes is not possible or requires a wrapper of sorts. And then of course tool support varies but that's FPGA dev!