Big Trouble at 3nm
semiengineering.com
semiengineering.com
Have the gate pitch / interconnect in the range of 40-54nm hit a more difficult limit than the 7nm aspect? It seems like there is significant space for improvement in those dimensions where you could still double density. Should process nodes be referred to as 7nm x 54nm where new generations drop gate pitch too?
Is there something inherent to the process that fixes the other dimensions when you have a "7nm" node for that particular metric?
From the article:
> The $1.5 billion figure involves a complex GPU at Nvidia
I think the graph shows how much it costs a company in total to design a chip at different nodes. In general, chip vendors add more functionality with each generation. That seems to be what the graph shows.
The article says the graph comes from International Business Strategies. Their web page tells me to install Flash, which was enough to prevent me looking further:
http://www.ibs-inc.net/#!reports
Also, someone should tell them that IBS stands for Irritable Bowel Syndrome.
It's decreasing wire resistance and gate capacitance. That's what makes the most difference. It is also about making things cheaper, because your costs are constant for a wafer, but the use is measured by gate count.
That said, things are not that simple for a long time already.
*Debatable: https://ieeexplore.ieee.org/document/7890390/