It is much more: Just to give examples:
- The introduction of the opmask registers to mask many AVX-512 instructions
- AVX-512 Conflict Detection Instructions (CD) enables lots of loops to vectorize that could not vectorized before.
Also the fact that now 32 SIMD registered can be addressed does not seem very innovative from the outside, but implies a deep change: Before only 8 (32 bit mode; bite 5-3 of MOD-REG-R/M field) or 16 (64 bit mode; additionally use REX.R field) SIMD registers could be addresses for deep instructional encoding reasons. This also holds when using a VEX prefix. So being able to use 32 SIMD registers requires a completely new prefix scheme (EVEX). This new scheme contains lots of new capabilities (source: https://en.wikipedia.org/w/index.php?title=AVX-512&oldid=841...):
- Expanded register encoding allowing 32 512-bit registers.
- Support up to 4 operands.
- Adds 7 new opmask registers for masking most AVX-512 instructions.
- Adds a new scalar memory mode that automatically performs a broadcast.
- Adds room for explicit rounding control in each instruction.
- Adds a new compressed displacement memory addressing mode.