Inside the 76477 Space Invaders sound effect chip
righto.com
righto.com
> One puzzling feature of the shift register is that there is no wiring between the stages!
> How do bits get from one stage to the next? Did the chip have another layer of wiring that wasn't in
> the photos? Was there some sort of hidden connection? Eventually I noticed that there wasn't an isolation
> ring between the stages—a silicon barrier that separated most I2L circuits. Without this isolation ring,
> an "invisible" PNP transistor exists between the stages, apparently allowing one stage to flip the next
> stage to the right value. Each shift-register stage is constructed from two NAND-gate latches. When the
> clock is low, the first latch is forced into an indeterminate state. When the clock goes high, the latch
> ends up as 0 or 1 based on the bias it receives from the previous stage through the "invisible" PNP
> transistors. Thus, the latch becomes edge-sensitive since it will change right on the clock's rising edge.
> I found a paper ("Injection-Coupled Synchronous Logic", 1978) that describes a similar technique for an I2L
> shift register9, so I think this is the right explanation, even though the circuit seems a bit sketchy.http://www.righto.com/2018/05/inside-76477-space-invaders-so...
One puzzling feature of the shift register is that there is no wiring between the stages! How do bits get from one stage to the next? Did the chip have another layer of wiring that wasn't in the photos? Was there some sort of hidden connection? Eventually I noticed that there wasn't an isolation ring between the stages—a silicon barrier that separated most I2L circuits. Without this isolation ring, an "invisible" PNP transistor exists between the stages, apparently allowing one stage to flip the next stage to the right value. Each shift-register stage is constructed from two NAND-gate latches. When the clock is low, the first latch is forced into an indeterminate state. When the clock goes high, the latch ends up as 0 or 1 based on the bias it receives from the previous stage through the "invisible" PNP transistors. Thus, the latch becomes edge-sensitive since it will change right on the clock's rising edge. I found a paper ("Injection-Coupled Synchronous Logic", 1978) that describes a similar technique for an I2L shift register9, so I think this is the right explanation, even though the circuit seems a bit sketchy.
For mobile, it helps if you manually truncate lines, like so:
One puzzling feature of the shift register
is that there is no wiring between the stages!
How do bits get from one stage to the next?
Did the chip have another layer of wiring that
wasn't in the photos? Was there some sort of
hidden connection? Eventually I noticed that
there wasn't an isolation ring between the
stages—a silicon barrier that separated most
I2L circuits. Without this isolation ring,
an "invisible" PNP transistor exists between
Mobile user here, your manual truncation was not enough unfortunately; it still gets cut off.
Leading white space is for code.
I wish everyone stopped making “blockquotes” with leading whitespace. It makes the text hard to read on mobile and it looks strange to have it in monospace font anyway.
Instead, prefix each paragraph of quoted text with the “>” but no leading whitespace and it’s clearly visible that you are quoting.
> One puzzling feature of the shift register is that there is no wiring between the stages! How do bits get from one stage to the next? Did the chip have another layer of wiring that wasn't in the photos? Was there some sort of hidden connection?
> Eventually I noticed that there wasn't an isolation ring between the stages—a silicon barrier that separated most I2L circuits.
> Without this isolation ring, an "invisible" PNP transistor exists between the stages, apparently allowing one stage to flip the next stage to the right value.
> Each shift-register stage is constructed from two NAND-gate latches. When the clock is low, the first latch is forced into an indeterminate state. When the clock goes high, the latch ends up as 0 or 1 based on the bias it receives from the previous stage through the "invisible" PNP transistors.
> Thus, the latch becomes edge-sensitive since it will change right on the clock's rising edge. I found a paper ("Injection-Coupled Synchronous Logic", 1978) that describes a similar technique for an I2L shift register9, so I think this is the right explanation, even though the circuit seems a bit sketchy.
Would it be that hard for the '1337 h4x04s at YC to support '>' blockquote markup like so many other forums?
As far as I can tell, formatdoc[0] doesn't provide a "semantically correct" method for formatting quotes. Hence, the age-old usenet quote (as codified in RFC3676[1]) seems to me to be the best way of indicating a quotation, and rendering it via a verbatim block ensures that the line-based quotation indication isn't disrupted by the text all being in a <p> tag when rendered in HTML.
[0] https://news.ycombinator.com/formatdoc [1] http://www.ietf.org/rfc/rfc3676.txt
[1] http://www.righto.com/2017/04/reverse-engineering-76477-spac...
Or I should find myself a Blacet Dark Star Chaos module. I should have bought one when I had the chance.
Covered this material to some extent, there are quite a few comments. This is a different article though by the same author.
Although it's not quite everything. The VCF is for noise only, and there's no way to insert a filter into the VCO audio path externally. However, that pretty much defines the "chip tune" genre.