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Comment by 1024core | Hacker News Reader

So what can you do with 1.15M logic gates that are in that FPGA? Can you, say, multiply, say 2 256x256 FP32 matrices?

Five top comments in and you're the first to ask the this question. Given how exotic this piece of silicon is I'd love to know too. This is the Intel webpage I found[0]. From there there's a link to an Altera page[1]. This is the marketing blurb that Anandtech got some of there info from[2].

A number of obvious interesting applications jump out at me: crypto acceleration for mining, machine learning acceleration, JIT acceleration for interpreted languages… How doable is all this? Would you have to roll your own code or are there libraries?

Wrt interpreted languages, I use Ruby fairly often and now that there's MRuby[3] I wonder if Ruby could be made run blazingly fast on something like this Xeon+FPGA thing?

Oh to have a spare $€£￥ to get me one of these.

[0] https://www.intel.com/content/www/us/en/servers/accelerators...

[1] https://www.altera.com/solutions/acceleration-hub/accelerati...

[2] https://itpeernetwork.intel.com/intel-processors-fpga-better...

[3] https://github.com/mruby/mruby

Top of the line Arria-10 FPGAs have about 1500 floating point MACs [1]. Using such a device, Intel claims ~1 TFLOP sustained for GEMM, the standard matrix multiply operation [2].

[1] https://www.altera.com/content/dam/altera-www/global/en_US/p...

[2] https://www.altera.com/content/dam/altera-www/global/en_US/p...

I would give a very strong health warning about taking those numbers seriously. What that 2nd reference doesn't make clear is that it is NOT a standard Matrix Multiply Operation, it's an 11 row by 16 column Matrix Multiplication.

This is important because unlike in software where performance scales well. For FPGA you would have to decompose every matrix multiplication into 11x16 style matrix multiplies. They don't mention this overhead in their specs.

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